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1. general description the TDA9983B is an hdmi transmitter (which also supports dvi) that enables a 3 8-bit rgb or yc b c r video stream (with a pixel rate up to 150 mhz for the TDA9983Bhw/15 version), up to 4 i 2 s-bus audio streams (with an audio sampling rate up to 192 khz) and the additional information required by all the hdmi 1.2a standards. a programmable upscaling block enables a 720p/1080i output from a standard de?nition input. an intra?eld deinterlacer is included in the scaler. in order to be compatible with most applications, the TDA9983B integrates a full programmable input formatter and color space conversion block. the video input formats accepted are yc b c r 4 : 4 : 4 (up to 3 8-bit), yc b c r 4:2:2 semi-planar (up to 2 12-bit), yc b c r 4 : 2 : 2 compliant with itu656 and itu656-like (up to 1 12-bit). for itu656-like formats, double edges are supported so that data can be sampled on rising and falling edges. the device can be controlled via an i 2 c-bus interface. 2. features n 3 8-bit video data input bus, cmos and lv-ttl compatible n horizontal synchronization, vertical synchronization and data enable (de) inputs or vref, href and fref could be used for input data synchronization n pixel rate clock input can be made active on one or both edges (selectable by i 2 c-bus) n the TDA9983B has 4 i 2 s-bus audio input channels and 1 s/pdif channel; audio sampling rate up to 192 khz n 250 mhz to 1.50 ghz hdmi transmitter operation n programmable input formatter and upsampler/interpolator allows input of any of the 4:4:4, 4:2:2 semi-planar, 4:2:2 itu656 and itu656-like formats n programmable color space converter: u rgb to yc b c r u yc b c r to rgb n the upscaler enables a 720p/1080i output from a standard de?nition input using intelligent edge interpolation n controllable via i 2 c-bus n low power dissipation n 1.8 v and 3.3 v power supplies n power-down mode TDA9983B hdmi transmitter up to 150 mhz pixel rate with 3 8-bit video inputs and 4 i 2 s-bus with s/pdif rev. 01 20 may 2008 product data sheet
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 2 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter n hard reset 3. applications n dvd players and recorders n set-top box (stb) n av receivers and ampli?ers (repeater) n camcorders n digital still cameras n media players n pvrs n media centers pcs, graphics add-in boards, notebook pcs n switches 4. quick reference data table 1. quick reference data v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 70 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit TDA9983Bhw/8 and TDA9983Bhw/15 v dda(fro_3v3) free running oscillator 3.3 v analog supply voltage 3.0 3.3 3.6 v v dda(pll_3v3) pll 3.3 v analog supply voltage 3.0 3.3 3.6 v v ddd(3v3) digital supply voltage (3.3 v) [1] 3.0 3.3 3.6 v v ddh(3v3) hdmi supply voltage (3.3 v) 3.0 3.3 3.6 v v ddc(1v8) core supply voltage (1.8 v) [1] 1.65 1.8 1.95 v t amb ambient temperature 0 - 70 c TDA9983Bhw/8; up to 81 mhz f clk(max) maximum clock frequency [2] 81 - - mhz p cons power consumption [2] - 322 - mw worst case [3] - 338 503 mw p tot total power dissipation [2] - 458 - mw worst case [3] - 472 651 mw p pd power dissipation in power-down mode - 13.5 38.4 mw
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 3 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] the v ddd(3v3) and v ddc(1v8) power supplies must always follow the sequence shown in figure 14 to ensure proper power-up conditions. [2] video format: a) input 480p (itu656 embedded sync, rising edge) b) output 1080i (yc b c r 4 : 2 : 2) [3] worst case video format: a) input 480p (yc b c r 4 : 2 : 2 semi-planar) b) output 720p (yc b c r 4 : 2 : 2) [4] video format: a) input 1080p (rgb 4 : 4 : 4 external sync, rising edge) b) output 1080p (rgb 4 : 4 : 4) 5. ordering information 5.1 ordering options TDA9983Bhw/15; up to 150 mhz f clk(max) maximum clock frequency [4] 150 - - mhz p cons power consumption [4] - 361 583 mw p tot total power dissipation [4] - 495 732 mw p pd power dissipation in power-down mode - 13.5 38.4 mw table 1. quick reference data continued v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 70 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 2. ordering information type number package name description version TDA9983Bhw htqfp80 plastic thermal enhanced thin quad ?at package; 80 leads; body 12 12 1 mm; exposed die pad sot841-4 table 3. survey of type numbers extended type number sampling frequency (msample/s) application TDA9983Bhw/8/c1 81 customer speci?c version TDA9983Bhw/15/c1 150 customer speci?c version
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 4 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 6. block diagram (1) block can be bypassed. fig 1. block diagram 001aag248 vpa[7:0] video input processor upscaler (1) video processing 3 8-bit rgb yc b c r 4 : 4 : 4 2 12-bit or 1 12-bit yc b c r 4 : 2 : 2 itu656 or itu656-like upsampling from 4 : 2 : 2 to 4 : 4 : 4 (1) downsampling from 4 : 4 : 4 to 4 : 2 : 2 (1) color space converter rgb to yuv yuv to rgb (4 : 4 : 4) (1) deinterlacer intrafield (1) TDA9983B audio processing hpd management data island packet information frames and packets vpb[7:0] vpc[7:0] vsync/vref hsync/href de/fref vclk 2 1 80 68 to 70, 75 to 79 57 and 58, 61 to 65, 67 49 to 56 66 hpd hdmi serializer 26 txc - 27 txc+ 29 tx0 - 30 tx0+ 32 tx1 - 33 tx1+ 35 tx2 - 36 tx2+ ddc_scl ddc_sda 20 19 int 17 i 2 c-bus slave ddc-bus irq generation i2c_scl i2c_sda a0 a1 43 44 41 40 ap7 to ap0 4 to 11 aclk 12 18 v ssd 14, 47, 72 v ssc 15, 60, 73 v ssa(fro_3v3) 22 v ssa(pll_3v3) 39 tm 21 ext_swing 24 v ssh 25, 31, 37 v ssa(pll_1v8) 46 hard reset rst_n 42 v pp v ddd(3v3) v ddc(1v8) v dda( fro_3v3) v ddh(3v3) v dda(pll_3v3) 3 13, 48, 71 16, 45, 59, 74 23 28, 34 38
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 5 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin con?guration TDA9983B hsync/href v ssc vsync/vref v ddc(1v8) v pp vpb[6] ap7 vpb[7] ap6 vpc[0] ap5 vpc[1] ap4 vpc[2] ap3 vpc[3] ap2 vpc[4] ap1 vpc[5] ap0 vpc[6] aclk vpc[7] v ddd(3v3) v ddd(3v3) v ssd v ssd v ssc v ssa(pll_1v8) v ddc(1v8) v ddc(1v8) int i2c_sda hpd i2c_scl ddc_sda rst_n ddc_scl a0 tm de/fref v ssa(fro_3v3) vpa[0] v dda(fro_3v3) vpa[1] ext_swing vpa[2] v ssh vpa[3] txc - vpa[4] txc+ v ddc(1v8) v ddh(3v3) v ssc tx0 - v ssd tx0+ v ddd(3v3) v ssh vpa[5] tx1 - vpa[6] tx1+ vpa[7] v ddh(3v3) vpb[0] tx2 - vclk tx2+ vpb[1] v ssh vpb[2] v dda(pll_3v3) vpb[3] v ssa(pll_3v3) vpb[4] a1 vpb[5] 001aag249 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 table 4. pin description symbol pin type [1] description hsync/href 1 i horizontal synchronization or reference input vsync/vref 2 i vertical synchronization or reference input v pp 3 p programming voltage (must be connected to the ground of the digital core in normal operation) ap7 4 i audio port 7 input; auxiliary (aux) ap6 5 i audio port 6 input; s/pdif stream ap5 6 i audio port 5 input; optional master clock mclk for s/pdif
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 6 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter ap4 7 i audio port 4 input; i 2 s-bus 3 ap3 8 i audio port 3 input; i 2 s-bus 2 ap2 9 i audio port 2 input; i 2 s-bus 1 ap1 10 i audio port 1 input; i 2 s-bus 0 ap0 11 i audio port 0 input; word select ws for i 2 s-bus aclk 12 i audio clock input; clock sck for i 2 s-bus v ddd(3v3) 13 p supply voltage for input ports (3.3 v) v ssd 14 g ground for input ports v ssc 15 g ground for digital core v ddc(1v8) 16 p supply voltage for digital core (1.8 v) int 17 o interrupt output (open drain); warns the external microprocessor that a special event has occurred; must be connected to a pull-up resistor; 5 v tolerant hpd 18 i hot plug detect input; 5 v tolerant ddc_sda 19 i/o ddc-bus data input/output (open drain); must be connected to a pull-up resistor; 5 v tolerant ddc_scl 20 o ddc-bus clock output (open drain); must be connected to a pull-up resistor; 5 v tolerant tm 21 i internal test mode input (must be connected to the ground of the digital core in normal operation) v ssa(fro_3v3) 22 g analog ground for free running oscillator v dda(fro_3v3) 23 p analog supply voltage for free running oscillator (3.3 v) ext_swing 24 i external swing adjust input; a ?xed resistor must be connected between this pin and v ddh(3v3) to set the hdmi output swing (see section 8.14.1 ) v ssh 25 g ground for hdmi transmitter txc - 26 o negative clock channel for hdmi output txc+ 27 o positive clock channel for hdmi output v ddh(3v3) 28 p supply voltage for hdmi transmitter (3.3 v) tx0 - 29 o negative data channel 0 for hdmi output tx0+ 30 o positive data channel 0 for hdmi output v ssh 31 g ground for hdmi transmitter tx1 - 32 o negative data channel 1 for hdmi output tx1+ 33 o positive data channel 1 for hdmi output v ddh(3v3) 34 p supply voltage for hdmi transmitter (3.3 v) tx2 - 35 o negative data channel 2 for hdmi output tx2+ 36 o positive data channel 2 for hdmi output v ssh 37 g ground for hdmi transmitter v dda(pll_3v3) 38 p analog supply voltage for pll (3.3 v) v ssa(pll_3v3) 39 g analog ground reference for pll a1 40 i i 2 c-bus slave address input 1; bit 1 a0 41 i i 2 c-bus slave address input 0; bit 0 rst_n 42 i hard reset input; active low table 4. pin description continued symbol pin type [1] description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 7 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter i2c_scl 43 i i 2 c-bus clock input of device (open drain); must be connected to a pull-up resistor; 5 v tolerant i2c_sda 44 i/o i 2 c-bus data input/output of device; open drain; must be connected to a pull-up resistor; 5 v tolerant v ddc(1v8) 45 p supply voltage for digital core (1.8 v) v ssa(pll_1v8) 46 g analog ground reference for pll v ssd 47 g ground for input ports v ddd(3v3) 48 p supply voltage for input ports (3.3 v) vpc[7] 49 i video port c input bit 7 vpc[6] 50 i video port c input bit 6 vpc[5] 51 i video port c input bit 5 vpc[4] 52 i video port c input bit 4 vpc[3] 53 i video port c input bit 3 vpc[2] 54 i video port c input bit 2 vpc[1] 55 i video port c input bit 1 vpc[0] 56 i video port c input bit 0 vpb[7] 57 i video port b input bit 7 vpb[6] 58 i video port b input bit 6 v ddc(1v8) 59 p supply voltage for digital core (1.8 v) v ssc 60 g ground for digital core vpb[5] 61 i video port b input bit 5 vpb[4] 62 i video port b input bit 4 vpb[3] 63 i video port b input bit 3 vpb[2] 64 i video port b input bit 2 vpb[1] 65 i video port b input bit 1 vclk 66 i video pixel clock input vpb[0] 67 i video port b input bit 0 vpa[7] 68 i video port a input bit 7 vpa[6] 69 i video port a input bit 6 vpa[5] 70 i video port a input bit 5 v ddd(3v3) 71 p supply voltage for input ports (3.3 v) v ssd 72 g ground for input ports v ssc 73 g ground for digital core v ddc(1v8) 74 p supply voltage for digital core (1.8 v) vpa[4] 75 i video port a input bit 4 vpa[3] 76 i video port a input bit 3 vpa[2] 77 i video port a input bit 2 vpa[1] 78 i video port a input bit 1 vpa[0] 79 i video port a input bit 0 de/fref 80 i video data enable input or ?eld reference input exposed die pad central g exposed die pad; must be connected to the ground of the hdmi transmitter (v ssh ) table 4. pin description continued symbol pin type [1] description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 8 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] p = power supply; g = ground; i = input; o = output. 8. functional description the TDA9983B is designed to convert digital data (video and audio) into an hdmi or a dvi stream. this hdmi stream can handle rgb, yc b c r 4:4:4andyc b c r 4:2:2.the TDA9983B can accept at its inputs any of the following video modes: ? rgb ? yc b c r 4:4:4 ? yc b c r 4 : 2 : 2 semi-planar ? yc b c r 4 : 2 : 2 itu656 and itu656-like it can also handle audio. the TDA9983B can accept at its inputs any of the following audio buses: ? i 2 s-bus (4 lines): up to 8 audio channels ? s/pdif (1 channel): l-pcm (iec 60958) or compressed audio (iec 61937) 8.1 system clock the clock management is based on a set of 3 plls that generate the different clocks required inside the chip. this includes: ? pll double edge can generate a clock at twice the vclk input frequency to capture the data at the video input formatter ? pll scaling can create a new video processing scaled clock taking into account the scaling ratio programmed in the scaler ? pll serializer is a system clock generator, which enables the stream produced by the encoder to be transmitted on the hdmi data channel at ten times the sampling rate or more; see section 8.14.2 8.2 video input processor the TDA9983B has three video input ports vpa[7:0], vpb[7:0] and vpc[7:0]. the TDA9983B can reallocate and swap each of the 3 ports input channels by inverting the bus and swapping each port. the TDA9983B can be set to latch data at either the rising or falling edge or both. the video input formats accept (see t ab le 5 ): ? rgb ? yc b c r 4 : 4 : 4 (up to 3 8-bit) ? yc b c r 4 : 2 : 2 semi-planar (up to 2 12-bit) ? yc b c r 4 : 2 : 2 compliant with itu656 and itu656-like (up to 1 12-bit)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 9 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] double edge means both rising and falling edges. table 5. inputs of video input formatter color space format channels sync rising edge falling edge double edge [1] transmission input format max. pixel clock on pin vclk (mhz) max. input format reference rgb 4:4:4 3 8-bit external x 150 t ab le 6 external x 150 embedded x 150 embedded x 150 yc b c r 4:4:4 3 8-bit external x 150 t ab le 7 external x 150 embedded x 150 embedded x 150 yc b c r 4:2:2 up to 1 12-bit itu656-like external x itu656-like 54.054 480p/576p t ab le 8 external x itu656-like 54.054 480p/576p external x itu656-like 27.027 480p/576p t ab le 9 embedded x itu656-like 54.054 480p/576p t ab le 10 embedded x itu656-like 54.054 480p/576p embedded x itu656-like 27.027 480p/576p t ab le 11 up to 2 12-bit semi-planar external x 148.5 1080p t ab le 12 external x 148.5 1080p embedded x smpte293m 148.5 1080p t ab le 13 embedded x smpte293m 148.5 1080p
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 10 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 6. rgb 4 :4:4 mappings rgb 4:4:4 (3 8-bit) external synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 45h; vip_cntrl_2 = 01h. video port a video port b video port c control pin rgb 4 : 4 : 4 pin rgb 4 : 4 : 4 pin rgb 4 : 4 : 4 pin rgb 4 :4:4 vpa[0] b[0] vpb[0] g[0] vpc[0] r[0] hsync/href used vpa[1] b[1] vpb[1] g[1] vpc[1] r[1] vsync/vref used vpa[2] b[2] vpb[2] g[2] vpc[2] r[2] de/fref used vpa[3] b[3] vpb[3] g[3] vpc[3] r[3] vpa[4] b[4] vpb[4] g[4] vpc[4] r[4] vpa[5] b[5] vpb[5] g[5] vpc[5] r[5] vpa[6] b[6] vpb[6] g[6] vpc[6] r[6] vpa[7] b[7] vpb[7] g[7] vpc[7] r[7] de could also be generated from hsync/href and vsync/vref fig 3. pixel encoding in rgb 4:4:4 (rising edge) input 001aag380 bxxx bxxx ... b3 b2 b1 b0 hsync/href vsync/vref de/fref gxxx gxxx ... g3 g2 g1 g0 rxxx rxxx ... r3 r2 r1 r0 control inputs vpa[7:0] vclk vpb[7:0] vpc[7:0]
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 11 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 7. yc b c r 4:4:4 mappings yc b c r 4:4:4 (3 8-bit) external synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 45h; vip_cntrl_2 = 01h. video port a video port b video port c control pin yc b c r 4:4:4 pin yc b c r 4:4:4 pin yc b c r 4:4:4 pin yc b c r 4:4:4 vpa[0] c b [0] vpb[0] y[0] vpc[0] c r [0] hsync/href used vpa[1] c b [1] vpb[1] y[1] vpc[1] c r [1] vsync/vref used vpa[2] c b [2] vpb[2] y[2] vpc[2] c r [2] de/fref used vpa[3] c b [3] vpb[3] y[3] vpc[3] c r [3] vpa[4] c b [4] vpb[4] y[4] vpc[4] c r [4] vpa[5] c b [5] vpb[5] y[5] vpc[5] c r [5] vpa[6] c b [6] vpb[6] y[6] vpc[6] c r [6] vpa[7] c b [7] vpb[7] y[7] vpc[7] c r [7] de could also be generated from hsync/href and vsync/vref fig 4. pixel encoding in yc b c r 4 : 4 : 4 (rising edge) input 001aag381 c b xxx c b xxx ... c b 3 c b 2 c b 1 c b 0 hsync/href vsync/vref de/fref yxxx yxxx ... y3 y2 y1 y0 c r xxx c r xxx ... c r 3 c r 2 c r 1 c r 0 control inputs vpa[7:0] vclk vpb[7:0] vpc[7:0]
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 12 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 8. yc b c r 4:2:2 itu656-like external synchronization single edge mappings yc b c r 4:2:2 itu656-like external synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. video port a video port b control pin yc b c r 4 : 2 : 2 (itu656-like) pin yc b c r 4 : 2 : 2 (itu656-like) pin yc b c r 4:2:2 vpa[0] c b [0] y 0 [0] c r [0] y 1 [0] vpb[0] c b [4] y 0 [4] c r [4] y 1 [4] hsync/href used vpa[1] c b [1] y 0 [1] c r [1] y 1 [1] vpb[1] c b [5] y 0 [5] c r [5] y 1 [5] vsync/vref used vpa[2] c b [2] y 0 [2] c r [2] y 1 [2] vpb[2] c b [6] y 0 [6] c r [6] y 1 [6] de/fref used vpa[3] c b [3] y 0 [3] c r [3] y 1 [3] vpb[3] c b [7] y 0 [7] c r [7] y 1 [7] vpa[4] - - - - vpb[4] c b [8] y 0 [8] c r [8] y 1 [8] vpa[5] - - - - vpb[5] c b [9] y 0 [9] c r [9] y 1 [9] vpa[6] - - - - vpb[6] c b [10] y 0 [10] c r [10] y 1 [10] vpa[7] - - - - vpb[7] c b [11] y 0 [11] c r [11] y 1 [11] fig 5. pixel encoding yc b c r 4 : 2 : 2 itu656-like external synchronization single edge (rising edge) input 001aag383 c r xxx yxxx ... y1 c r 0 y0 c b 0 hsync/href vsync/vref de/fref control inputs vpb[7:0]; vpa[3:0] vclk
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 13 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 9. yc b c r 4:2:2 itu656-like external synchronization double edge mappings yc b c r 4:2:2 itu656-like external synchronization double edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. video port a video port b control pin yc b c r 4 : 2 : 2 (itu656-like) pin yc b c r 4 : 2 : 2 (itu656-like) pin yc b c r 4:2:2 vpa[0] c b [0] y 0 [0] c r [0] y 1 [0] vpb[0] c b [4] y 0 [4] c r [4] y 1 [4] hsync/href used vpa[1] c b [1] y 0 [1] c r [1] y 1 [1] vpb[1] c b [5] y 0 [5] c r [5] y 1 [5] vsync/vref used vpa[2] c b [2] y 0 [2] c r [2] y 1 [2] vpb[2] c b [6] y 0 [6] c r [6] y 1 [6] de/fref used vpa[3] c b [3] y 0 [3] c r [3] y 1 [3] vpb[3] c b [7] y 0 [7] c r [7] y 1 [7] vpa[4] - - - - vpb[4] c b [8] y 0 [8] c r [8] y 1 [8] vpa[5] - - - - vpb[5] c b [9] y 0 [9] c r [9] y 1 [9] vpa[6] - - - - vpb[6] c b [10] y 0 [10] c r [10] y 1 [10] vpa[7] - - - - vpb[7] c b [11] y 0 [11] c r [11] y 1 [11] fig 6. pixel encoding yc b c r 4 : 2 : 2 itu656-like external synchronization double edge (rising and falling) input 001aag382 c r xxx yxxx ... y1 c r 0 y0 c b 0 hsync/href vsync/vref de/fref vpb[7:0]; vpa[3:0] vclk control inputs
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 14 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 10. yc b c r 4:2:2 itu656-like embedded synchronization single edge mappings yc b c r 4:2:2 itu656-like embedded synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. video port a video port b control pin yc b c r 4 : 2 : 2 (itu656-like) pin yc b c r 4 : 2 : 2 (itu656-like) pin yc b c r 4:2:2 vpa[0] c b [0] y 0 [0] c r [0] y 1 [0] vpb[0] c b [4] y 0 [4] c r [4] y 1 [4] hsync/href not used vpa[1] c b [1] y 0 [1] c r [1] y 1 [1] vpb[1] c b [5] y 0 [5] c r [5] y 1 [5] vsync/vref not used vpa[2] c b [2] y 0 [2] c r [2] y 1 [2] vpb[2] c b [6] y 0 [6] c r [6] y 1 [6] de/fref not used vpa[3] c b [3] y 0 [3] c r [3] y 1 [3] vpb[3] c b [7] y 0 [7] c r [7] y 1 [7] vpa[4] - - - - vpb[4] c b [8] y 0 [8] c r [8] y 1 [8] vpa[5] - - - - vpb[5] c b [9] y 0 [9] c r [9] y 1 [9] vpa[6] - - - - vpb[6] c b [10] y 0 [10] c r [10] y 1 [10] vpa[7] - - - - vpb[7] c b [11] y 0 [11] c r [11] y 1 [11] fig 7. pixel encoding yc b c r 4 : 2 : 2 itu656-like embedded synchronization single edge (rising edge) input 001aag385 c r xxx yxxx ... y1 c r 0 y0 c b 0 vpb[7:0]; vpa[3:0] vclk
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 15 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 11. yc b c r 4:2:2 itu656-like embedded synchronization double edge mappings yc b c r 4:2:2 itu656-like embedded synchronization double edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. video port a video port b control pin yc b c r 4 : 2 : 2 (itu656-like) pin yc b c r 4 : 2 : 2 (itu656-like) pin yc b c r 4:2:2 vpa[0] c b [0] y 0 [0] c r [0] y 1 [0] vpb[0] c b [4] y 0 [4] c r [4] y 1 [4] hsync/href not used vpa[1] c b [1] y 0 [1] c r [1] y 1 [1] vpb[1] c b [5] y 0 [5] c r [5] y 1 [5] vsync/vref not used vpa[2] c b [2] y 0 [2] c r [2] y 1 [2] vpb[2] c b [6] y 0 [6] c r [6] y 1 [6] de/fref not used vpa[3] c b [3] y 0 [3] c r [3] y 1 [3] vpb[3] c b [7] y 0 [7] c r [7] y 1 [7] vpa[4] - - - - vpb[4] c b [8] y 0 [8] c r [8] y 1 [8] vpa[5] - - - - vpb[5] c b [9] y 0 [9] c r [9] y 1 [9] vpa[6] - - - - vpb[6] c b [10] y 0 [10] c r [10] y 1 [10] vpa[7] - - - - vpb[7] c b [11] y 0 [11] c r [11] y 1 [11] fig 8. pixel encoding yc b c r 4 : 2 : 2 itu656-like embedded synchronization double edge (rising and falling) input 001aag384 c r xxx yxxx ... y1 c r 0 y0 c b 0 vpb[7:0]; vpa[3:0] vclk
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 16 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 12. yc b c r 4:2:2 semi-planar external synchronization mappings yc b c r 4:2:2 semi-planar external synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 14h. video port a video port b video port c control pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 vpa[0] y 0 [0] y 1 [0] vpb[0] y 0 [4] y 1 [4] vpc[0] c b [4] c r [4] hsync/href used vpa[1] y 0 [1] y 1 [1] vpb[1] y 0 [5] y 1 [5] vpc[1] c b [5] c r [5] vsync/vref used vpa[2] y 0 [2] y 1 [2] vpb[2] y 0 [6] y 1 [6] vpc[2] c b [6] c r [6] de/fref used vpa[3] y 0 [3] y 1 [3] vpb[3] y 0 [7] y 1 [7] vpc[3] c b [7] c r [7] vpa[4] c b [0] c r [0] vpb[4] y 0 [8] y 1 [8] vpc[4] c b [8] c r [8] vpa[5] c b [1] c r [1] vpb[5] y 0 [9] y 1 [9] vpc[5] c b [9] c r [9] vpa[6] c b [2] c r [2] vpb[6] y 0 [10] y 1 [10] vpc[6] c b [10] c r [10] vpa[7] c b [3] c r [3] vpb[7] y 0 [11] y 1 [11] vpc[7] c b [11] c r [11] fig 9. pixel encoding yc b c r 4 : 2 : 2 semi-planar external synchronization (rising edge) input 001aag386 y5 ... y4 y3 y2 y1 y0 hsync/href vsync/vref de/fref c r 4 ... c b 4 c r 2 c b 2 c r 0 c b 0 control inputs vpb[7:0]; vpa[3:0] vclk vpc[7:0]; vpa[7:4]
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 17 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 13. yc b c r 4:2:2 semi-planar embedded synchronization mappings yc b c r 4:2:2 semi-planar embedded synchronization single edge. register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 14h. video port a video port b video port c control pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 semi-planar pin yc b c r 4:2:2 vpa[0] y 0 [0] y 1 [0] vpb[0] y 0 [4] y 1 [4] vpc[0] c b [4] c r [4] hsync/href not used vpa[1] y 0 [1] y 1 [1] vpb[1] y 0 [5] y 1 [5] vpc[1] c b [5] c r [5] vsync/vref not used vpa[2] y 0 [2] y 1 [2] vpb[2] y 0 [6] y 1 [6] vpc[2] c b [6] c r [6] de/fref not used vpa[3] y 0 [3] y 1 [3] vpb[3] y 0 [7] y 1 [7] vpc[3] c b [7] c r [7] vpa[4] c b [0] c r [0] vpb[4] y 0 [8] y 1 [8] vpc[4] c b [8] c r [8] vpa[5] c b [1] c r [1] vpb[5] y 0 [9] y 1 [9] vpc[5] c b [9] c r [9] vpa[6] c b [2] c r [2] vpb[6] y 0 [10] y 1 [10] vpc[6] c b [10] c r [10] vpa[7] c b [3] c r [3] vpb[7] y 0 [11] y 1 [11] vpc[7] c b [11] c r [11] fig 10. pixel encoding yc b c r 4 : 2 : 2 semi-planar embedded synchronization (rising edge) input 001aag387 y5 ... y4 y3 y2 y1 y0 c r 4 ... c b 4 c r 2 c b 2 c r 0 c b 0 vpb[7:0]; vpa[3:0] vclk vpc[7:0]; vpa[7:4]
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 18 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 8.3 synchronization the TDA9983B can be synchronized with hsync/vsync external inputs or with extraction of the sync information from embedded sync (sav/eav) codes inside the video stream. 8.3.1 timing extraction generator this block can extract the synchronization signals href, vref and fref from start active video (sav) and end active video (eav) in case of embedded synchronization in the data stream. synchronization signals can be embedded in rgb, yc b c r 4 : 4 : 4, yc b c r 4:2:2 semi-planar (up to 2 12-bit), yc b c r 4:2:2 itu656 and itu656-like (up to 1 12-bit). 8.3.2 data enable generator the TDA9983B contains a data enable (de) generator; this can generate an internal de signal for a system which does not provide one. 8.4 input and output video format due to the ?exible video input formatter, the TDA9983B can accept a large range of input formats. this ?exibility allows the TDA9983B to be compatible with the maximum possible number of mpeg decoders. moreover, these input formats may be changed in many ways (color space converter, upsampler, downsampler and scaler) to be transmitted across the hdmi link. t ab le 14 gives the possible inputs and outputs. 8.5 upsampler the incoming yc b c r 4 : 2 : 2 (2 12-bit) data stream format could be upsampled into a 12-bit yc b c r 4 : 4 : 4 (3 12-bit) data stream by repeating or linearly interpolating the chrominance pixels. table 14. use of color space converter, upsampler, downsampler and scaler input scaler output color space format channels color space format channels rgb 4:4:4 3 8-bit no scaling rgb 4:4:4 3 8-bit no scaling yc b c r 4:2:2 2 12-bit no scaling yc b c r 4:4:4 3 8-bit yc b c r 4:4:4 3 8-bit no scaling rgb 4:4:4 3 8-bit no scaling yc b c r 4:2:2 2 12-bit no scaling yc b c r 4:4:4 3 8-bit yc b c r 4 : 2 : 2 up to 1 12-bit scalable yc b c r 4:2:2 2 12-bit scalable yc b c r 4:4:4 3 8-bit scalable rgb 4:4:4 3 8-bit up to 2 12-bit scalable yc b c r 4:2:2 2 12-bit scalable yc b c r 4:4:4 3 8-bit scalable rgb 4:4:4 3 8-bit
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 19 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 8.6 color space converter the color space converter is used to convert input video data from one type to another color space (rgb to yc b c r and yc b c r to rgb). this block can be bypassed and each coef?cient is programmable via the i 2 c-bus register. 8.7 downsampler this block works only with yc b c r input format; these ?lters downsample the c b and c r signals by a factor 2. a delay is added on the g/y channel, which corresponds to the pipeline delay of the ?lters, to put the y channel in phase with the c b -c r channels. 8.8 audio input format the TDA9983B is compatible with hdmi 1.2a (dvd support). the TDA9983B can carry audio in i 2 s-bus format (one stereo up to four stereo channels) or in s/pdif format. s/pdif or i 2 s-bus format can be selected via the i 2 c-bus. only one audio format can be used at a time: either s/pdif or i 2 s-bus. t ab le 15 shows the audio port allocation. 8.9 s/pdif the audio port ap6 is used for the s/pdif feature. in this format the TDA9983B supports 2-channel uncompressed pcm data (iec 60958) layout 0 or compressed bit stream up to 8 multichannels (dolby digital, dts, ac-3, etc.) layout 1. the TDA9983B is able to recover the original clock from the s/pdif signal (no need for an external clock). in addition it can also use an external clock (mclk) to decode the s/pdif signal. 8.10 i 2 s-bus the TDA9983B supports the nxp i 2 s-bus format. there are four i 2 s-bus stereo input channels (ap1 to ap4), which enable 8 uncompressed audio channels to be carried. the i 2 s-bus input interface receives an i 2 s-bus signal including serial data, word select and y \ g c b \ r c r \ b c 11 c 12 c 13 c 21 c 22 c 23 c 31 c 32 c 33 g \ y r \ c b b \ c r oin g \ y oin r \ c b oin b \ c r + ? ? ? ? ? ?? oout y \ g oout c b \ r oout c r \ b + = table 15. audio port con?guration all audio ports are lv-ttl compatible. audio port i 2 s-bus and s/pdif input con?guration ap0 ws (word select) ap1 i 2 s-bus audio port 0 ap2 i 2 s-bus audio port 1 ap3 i 2 s-bus audio port 2 ap4 i 2 s-bus audio port 3 ap5 mclk (master clock for s/pdif) ap6 s/pdif input ap7 aux (internal test) aclk sck (i 2 s-bus clock)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 20 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter serial clock. various i 2 s-bus formats are supported and can be selected by setting the appropriate bits of the register. the i 2 s-bus input interface can receive up to 24-bit wide audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency f s . since the i 2 s-bus format is msb aligned, audio data with an arbitrary precision can be received automatically. audio samples with a precision better than 24 bits are truncated to 24 bits. if the input clock has a frequency of 32 f s , only 16-bit audio samples can be received. in this case, the 8 lsbs will be set to logic 0. the serial data signal carries the serial baseband audio data, sample by sample left/right interleaved. the word select signal ws indicates whether left or right channel information is transferred over the serial data line. the formats for 16-bit and 32-bit modes are shown in figure 11 . 8.11 power management the TDA9983B can be powered down via the i 2 c-bus register. 8.12 interrupt controller pin int is used to alert the microcontroller that a critical event concerning the hdmi has occurred (hot plug detect). this interrupt is maskable. hot plug or unplug detect: pin hpd is the hot plug detection pin; it is 5 v input tolerant. 8.13 initialization hard reset: after power-up, the TDA9983B is activated by a hard reset via pin rst_n. however, the TDA9983B has a power-on reset. a. 32-bit mode b. 16-bit mode fig 11. nxp i 2 s-bus formats 001aag915 ap0/ws aclk apx x = 1, 2, 3, 4 left channel right channel 0 r b23 l b0 l 0 l 0 l 0 l b23 r b0 r 0 r 0 r 0 r b23 l 001aag916 ap0/ws aclk apx x = 1, 2, 3, 4 left channel right channel b0 r b15 l b14 l b13 l b2 l b1 l b0 l b15 r b14 r b13 r b2 r b1 r b0 r b15 l
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 21 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 8.14 hdmi 8.14.1 output hdmi buffers an external resistor must be used to set the hdmi output amplitude. it has to be connected between pin ext_swing and v ddh(3v3) . 8.14.2 pixel repetition to transmit video formats with pixel rates below 25 msample/s or to increase the number of audio sample packets in each frame, the TDA9983B uses pixel repetition to increase the transmitted pixel clock. 8.14.3 hdmi and dvi receiver discrimination this information is located in the e-edid receiver part, in the vendor-speci?c data block within the ?rst cea edid timing extension. if the 24-bit ieee registration identi?er contains the value 00 0c03h, then the receiver will support hdmi, otherwise the device will be treated as a dvi device. however, the TDA9983B does not have direct access to that information since e-edid is read by an external microprocessor through the TDA9983B i 2 c-bus gate. 8.14.4 ddc channel the ddc-bus pins ddc_sda and ddc_scl are 5 v tolerant and can work at standard mode (100 khz). 8.14.4.1 e-edid reading in order to get receiver capabilities, the TDA9983B must read the e-edid of the receiver. this is made possible by temporarily connecting the i 2 c-bus to the ddc lines, so that the microprocessor is able to read full edid. 8.15 scaler unit the scaler unit has the following features: ? upscaling only: to expand input image horizontally and vertically table 16. pixel repetition srl_pr[3] srl_pr[2] srl_pr[1] srl_pr[0] pixel repeated 0000no repetition 0001 once 0010 twice 00113 times 01004 times 01015 times 01106 times 01117 times 10008 times 10019 times 101x unde?ned 1 1 x x unde?ned
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 22 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter ? embedded deinterlacer (no need for output memory) ? maximum output operating frequency: 74.5 mhz (hdtv supported 1080i, 720p) ? input video standards (yc b c r 4 : 2 : 2 semi-planar, itu656 and itu656-like yc b c r , no rgb and no yc b c r 4:4:4) 8.16 input and output video scaler the scaler converts the standard de?nition video signals (480i/576i, 480p/576p) into 720p, 1080i as illustrated in figure 12 . 8.17 i 2 c-bus interface the i 2 c-bus pins i2c_sda and i2c_scl are 5 v tolerant and can work at fast mode (400 khz). all upscaling modes are available only for yc b c r 4 : 2 : 2 input format. (1) pass through (2) upscaling (3) upscaling and interlacing (4) deinterlacing (5) deinterlacing and upscaling (6) deinterlacing, upscaling and interlacing fig 12. input and output video scaler 001aag258 720 1280 1920 720 1920 480p 720p 1080i 480i 1080p 2, 3 4 5 6, 7 (ntsc) 16 720 1280 1920 720 1920 576p 720p 1080i 576i 1080p 480p 720p 1080i 480i 1080p 720 1280 1920 720 1920 576p 720p 1080i 576i 1080p 720 1280 1920 720 1920 17, 18 19 20 21, 22 (pal) 31 2, 3 4 5 6, 7 (ntsc) 16 17, 18 19 20 21, 22 (pal) 31 video standard output video standard input format 861b format 861b (1) (1) (1) (1) (1) (1) (1) (2) (2) (3) (3) (1) (1) (6) (6) (5) (5) (4) (4) (1)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 23 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9. i 2 c-bus register de?nitions 9.1 i 2 c-bus protocol the registers of the TDA9983B can be accessed via the i 2 c-bus. the TDA9983B is used as a slave device and both the fast mode 400 khz and the standard mode 100 khz are supported. bits a0 and a1 of the i 2 c-bus device address are externally selected by pins a0 and a1. the i 2 c-bus device address is given in t ab le 17 . the i 2 c-bus access format is shown in figure 13 . for read access, the master writes the address of the TDA9983B, the subaddress to access the speci?c register and then the data. 9.2 memory page management the i 2 c-bus memory is split into several pages and the selection between pages is made with common register curpage_adr. it is only necessary to write in this register once to change the current page. so multiple read or write operations in the same page need a write register curpage_adr once at the beginning. 9.3 general control page register de?nitions the current page address for the general control page is 00h. the con?guration of the registers for this page is given in t ab le 19 . table 17. device address device address r/ w a6 a5 a4 a3 a2 a1 a0 - 1 1 1 0 0 a1 a0 1/0 fig 13. i 2 c-bus access 001aaf292 123456789123456789123456789 slave address subaddress scl sda data stop table 18. memory pages page address memory page description reference 00h general control see section 9.3 on page 23 01h scaler see section 9.4 on page 43 02h pll settings see section 9.5 on page 55 10h information frames and packets see section 9.6 on page 63 11h audio settings and content info packets see section 9.7 on page 81 12h hdmi and dvi see section 9.8 on page 98
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 24 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 19. i 2 c-bus registers of memory page 00h [1] register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb) version 00h r 0 1 100010 0110 0010 main_cntrl0 01h w scaler x x cehs cecs dehs decs sr 0000 0000 not used 02h - - 0000 0000 ::: : : not used 0eh - - 0000 0000 int_flags_0 0fh r/w x x xxxxhpdx 0000 0000 int_flags_1 10h r/w hpd_in x sc_deil sc_vid sc_out sc_in x vs_rpt 0000 0000 not used 11h - - 0000 0000 ::: : : not used 1fh - - 0000 0000 vip_cntrl_0 20h w mirr_a swap_a[2:0] mirr_b swap_b[2:0] 0000 0001 vip_cntrl_1 21h w mirr_c swap_c[2:0] mirr_d swap_d[2:0] 0010 0100 vip_cntrl_2 22h w mirr_e swap_e[2:0] mirr_f swap_f[2:0] 0101 0110 vip_cntrl_3 23h w edge x sp_sync[1:0] emb v_tgl h_tgl x_tgl 0001 0110 vip_cntrl_4 24h w tst_pat tst_656 x ccir656 blankit[1:0] blc[1:0] 0000 0001 vip_cntrl_5 25h w x x x x x sp_cnt[1:0] ckcase 0000 0000 not used 26h - - 0000 0000 ::: : : not used 7fh - - 0000 0000 mat_contrl 80h w x x x x x mat_bp mat_sc[1:0] 0000 0101 mat_oi1_msb 81h w x x x x x offset_in1[10:8] 0000 0000 mat_oi1_lsb 82h w offset_in1[7:0] 0000 0000 mat_oi2_msb 83h w x x x x x offset_in2[10:8] 0000 0110 mat_oi2_lsb 84h w offset_in2[7:0] 0000 0000 mat_oi3_msb 85h w x x x x x offset_in3[10:8] 0000 0110 mat_oi3_lsb 86h w offset_in3[7:0] 0000 0000 mat_p11_msb 87h w x x x x x p11[10:8] 0000 0010 mat_p11_lsb 88h w p11[7:0] 0000 0000 mat_p12_msb 89h w x x x x x p12[10:8] 0000 0110 mat_p12_lsb 8ah w p12[7:0] 1001 0010 mat_p13_msb 8bh w x x x x x p13[10:8] 0000 0111 mat_p13_lsb 8ch w p13[7:0] 0101 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 25 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter mat_p21_msb 8dh w x x x x x p21[10:8] 0000 0010 mat_p21_lsb 8eh w p21[7:0] 0000 0000 mat_p22_msb 8fh w x x x x x p22[10:8] 0000 0010 mat_p22_lsb 90h w p22[7:0] 1100 1110 mat_p23_msb 91h w x x x x x p23[10:8] 0000 0000 mat_p23_lsb 92h w p23[7:0] 0000 0000 mat_p31_msb 93h w x x x x x p31[10:8] 0000 0010 mat_p31_lsb 94h w p31[7:0] 0000 0000 mat_p32_msb 95h w x x x x x p32[10:8] 0000 0000 mat_p32_lsb 96h w p32[7:0] 0000 0000 mat_p33_msb 97h w x x x x x p33[10:8] 0000 0011 mat_p33_lsb 98h w p33[7:0] 1000 1100 mat_oo1_msb 99h w x x x x x offset_out1[10:8] 0000 0000 mat_oo1_lsb 9ah w offset_out1[7:0] 0000 0000 mat_oo2_msb 9bh w x x x x x offset_out2[10:8] 0000 0000 mat_oo2_lsb 9ch w offset_out2[7:0] 0000 0000 mat_oo3_msb 9dh w x x x x x offset_out3[10:8] 0000 0000 mat_oo3_lsb 9eh w offset_out3[7:0] 0000 0000 not used 9fh - - - ------ 0000 0000 vidformat a0h w x x x vidformat[4:0] 0000 0000 refpix_msb a1h w x x x preset_pix[12:8] 0000 0000 refpix_lsb a2h w preset_pix[7:0] 0000 0001 refline_msb a3h w x x x x x preset_line[10:8] 0000 0000 refline_lsb a4h w preset_line[7:0] 0000 0001 npix_msb a5h w x x x npix[12:8] 0000 0000 npix_lsb a6h w npix[7:0] 0000 0000 nline_msb a7h w x x x x x nline[10:8] 0000 0000 nline_lsb a8h w nline[7:0] 0000 0000 vs_line_strt_1_msb a9h w x x x x x vs_line_start_1[10:8] 0000 0000 vs_line_strt_1_lsb aah w vs_line_start_1[7:0] 0000 0000 vs_pix_strt_1_msb abh w x x x vs_pix_start_1[12:8] 0000 0000 vs_pix_strt_1_lsb ach w vs_pix_start_1[7:0] 0000 0000 table 19. i 2 c-bus registers of memory page 00h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 26 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter vs_line_end_1_msb adh w x x x x x vs_line_end_1[10:8] 0000 0000 vs_line_end_1_lsb aeh w vs_line_end_1[7:0] 0000 0000 vs_pix_end_1_msb afh w x x x vs_pix_end_1[12:8] 0000 0000 vs_pix_end_1_lsb b0h w vs_pix_end_1[7:0] 0000 0000 vs_line_strt_2_msb b1h w x x x x x vs_line_start_2[10:8] 0000 0000 vs_line_strt_2_lsb b2h w vs_line_start_2[7:0] 0000 0000 vs_pix_strt_2_msb b3h w x x x vs_pix_start_2[12:8] 0000 0000 vs_pix_strt_2_lsb b4h w vs_pix_start_2[7:0] 0000 0000 vs_line_end_2_msb b5h w x x x x x vs_line_end_2[10:8] 0000 0000 vs_line_end_2_lsb b6h w vs_line_end_2[7:0] 0000 0000 vs_pix_end_2_msb b7h w x x x vs_pix_end_2[12:8] 0000 0000 vs_pix_end_2_lsb b8h w vs_pix_end_2[7:0] 0000 0000 hs_pix_start_msb b9h w x x x hs_pix_start[12:8] 0000 0000 hs_pix_start_lsb bah w hs_pix_start[7:0] 0000 0000 hs_pix_stop_msb bbh w x x x hs_pix_end[12:8] 0000 0000 hs_pix_stop_lsb bch w hs_pix_end[7:0] 0000 0000 vwin_start_1_msb bdh w x x x x x vwin_start_1[10:8] 0000 0000 vwin_start_1_lsb beh w vwin_start_1[7:0] 0000 0000 vwin_end_1_msb bfh w x x x x x vwin_end_1[10:8] 0000 0000 vwin_end_1_lsb c0h w vwin_end_1[7:0] 0000 0000 vwin_start_2_msb c1h w x x x x x vwin_start_2[10:8] 0000 0000 vwin_start_2_lsb c2h w vwin_start_2[7:0] 0000 0000 vwin_end_2_msb c3h w x x x x x vwin_end_2[10:8] 0000 0000 vwin_end_2_lsb c4h w vwin_end_2[7:0] 0000 0000 de_start_msb c5h w x x x de_start[12:8] 0000 0000 de_start_lsb c6h w de_start[7:0] 0000 0000 de_stop_msb c7h w x x x de_end[12:8] 0000 0000 de_stop_lsb c8h w de_end[7:0] 0000 0000 colbar_width c9h w cbw[7:0] 0000 0000 tbg_cntrl_0 cah w sync_ once sync_ mthd frame_ dis xxxxx 0000 0000 tbg_cntrl_1 cbh w x dwin_dis vhx_ext[2:0] vh_tgl[2:0] 0000 0000 table 19. i 2 c-bus registers of memory page 00h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 27 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter vbl_offset_start cch w vbloff_start[7:0] 0000 0000 vbl_offset_end cdh w vbloff_end[7:0] 0000 0000 hbl_offset_start ceh w hbloff_start[7:0] 0000 0000 hbl_offset_end cfh w hbloff_end[7:0] 0000 0000 dwin_re_de d0h w dwin_re_de[7:0] 0001 0001 dwin_fe_de d1h w dwin_fe_de[7:0] 0111 1010 not used d2h - - 0000 0000 ::: : : not used e3h - - 0000 0000 hvf_cntrl_0 e4h w sm rwb x x prefil[1:0] intpol[1:0] 0000 0000 hvf_cntrl_1 e5h w x semi_ planar pad[1:0] vqr[1:0] yuvblk for 0x00 0000 not used e6h - - 0000 0000 not used e7h - - 0000 0000 timer_h e8h w im_ clksel wd_ clksel xxxx tim_h[1:0] xx00 0001 timer_m e9h w tim_m[7:0] 1100 0010 timer_l eah w tim_l[7:0] 0100 0000 not used ebh - - 0000 0000 ::: : : not used edh - - 0000 0000 ndiv_im eeh w x x x x ndiv_im[3:0] 0000 0011 ndiv_pf efh w ndif_pf[7:0] 0001 1011 rpt_cntrl f0h w x x x x repeat[3:0] 0000 0000 lead_off f1h w x x x x lead_offset[3:0] 0000 0010 trail_off f2h w x x x x trail_offset[3:0] 0000 0010 not used f3h - - 0000 0000 ::: : : not used f7h - - 0000 0000 for test f8h w x x xxxxxx 0000 0000 ghost_xaddr f9h w ghost_xaddr[6:0] a0_zero 0110 0000 not used fah - - - ------ 0000 0000 not used fbh - - - ------ 0000 0000 table 19. i 2 c-bus registers of memory page 00h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 28 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] r: reading register w: writing register x: bit must be set to default value for proper operation -: not used not used fch - - - ------ 0000 0000 aip_clksel fdh w x x x sel_aip[1:0] sel_pol_ clk sel_fs[1:0] 0000 0000 ghost_addr feh w ghost_addr[6:0] ghost_ dis 1010 0001 curpage_adr ffh w curpage_adr[7:0] 0000 0000 table 19. i 2 c-bus registers of memory page 00h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 29 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.3.1 main control register 9.3.2 interrupt ?ags/masks registers table 20. version register (address 00h) bit description legend: * = default value bit symbol access value description 7 to 4 - r 0110 TDA9983B device version 3 to 0 - r 0010 die version table 21. main_cntrl0 register (address 01h) bit description legend: * = default value bit symbol access value description 7 scaler w scaler 0* hdmi video formatter uses vip-output (scaler is bypassed) 1 hdmi video formatter uses scaler-output 6 to 5 x w 00* unde?ned 4 cehs w i 2 c-bus enable high speed 0* i2c_sda and i2c_scl set to standard or fast mode 1 i2c_sda and i2c_scl set to high-speed mode 3 cecs w i 2 c-bus enable current source 0* i2c_scl pull-up current source disabled 1 i2c_scl pull-up current source enabled 2 dehs w ddc-bus enable high speed 0* ddc_sda and ddc_scl set to standard or fast mode 1 ddc_sda and ddc_scl set to high-speed mode 1 decs w ddc-bus enable current source 0* ddc_scl pull-up current source disabled 1 ddc_scl pull-up current source enabled 0sr w soft reset 0* no speci?c action 1 soft reset for all modules which do not use the cclk clock domain table 22. int_flags_0 register (address 0fh) bit description legend: * = default value bit symbol access value description 7 to 2 x r/w 0000 00* unde?ned 1 hpd r/w hpd: transition on hpd input 0* false/int_disabled 1 true/int_enabled 0 x r/w 0* unde?ned
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 30 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.3.3 video input processing control registers table 23. int_flags_1 register (address 10h) bit description legend: * = default value bit symbol access value description 7 hpd_in r/w hpd input: transition on hpd input 0* hpd is low 1 hpd is high 6 x r/w 0* unde?ned 5 sc_deil r/w scaler deinterlace: scaler deinterlaced video buffer failure 0* false/int_disabled 1 true/int_enabled 4 sc_vid r/w scaler video: scaler primary video buffer full failure 0* false/int_disabled 1 true/int_enabled 3 sc_out r/w scaler output: scaler output failure 0* false/int_disabled 1 true/int_enabled 2 sc_in r/w scaler input : scaler input failure 0* false/int_disabled 1 true/int_enabled 1 x r/w 0* unde?ned 0 vs_rpt r/w rising edge on vs_rpt detected 0* false/int_disabled 1 true/int_enabled table 24. vip_cntrl_0 register (address 20h) bit description legend: * = default value bit symbol access value description 7 mirr_a w mirror a 0* no speci?c action 1 mirror nibble; m[23:20] = s[20:23] 6 to 4 swap_a[2:0] w swap a selector 000* pin vpc[7:4] = vp[23:20] 001 pin vpc[3:0] = vp[23:20] 010 pin vpb[7:4] = vp[23:20] 011 pin vpb[3:0] = vp[23:20] 100 pin vpa[7:4] = vp[23:20] other pin vpa[3:0] = vp[23:20] 3 mirr_b w mirror b 0* no speci?c action 1 mirror nibble; m[19:16] = s[16:19]
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 31 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 2 to 0 swap_b[2:0] w swap b selector 000 pin vpc[7:4] = vp[19:16] 001* pin vpc[3:0] = vp[19:16] 010 pin vpb[7:4] = vp[19:16] 011 pin vpb[3:0] = vp[19:16] 100 pin vpa[7:4] = vp[19:16] other pin vpa[3:0] = vp[19:16] table 25. vip_cntrl_1 register (address 21h) bit description legend: * = default value bit symbol access value description 7 mirr_c w mirror c 0* no speci?c action 1 mirror nibble; m[15:12] = s[12:15] 6 to 4 swap_c[2:0] w swap c selector 000 pin vpc[7:4] = vp[15:12] 001 pin vpc[3:0] = vp[15:12] 010* pin vpb[7:4] = vp[15:12] 011 pin vpb[3:0] = vp[15:12] 100 pin vpa[7:4] = vp[15:12] other pin vpa[3:0] = vp[15:12] 3 mirr_d w mirror d 0* no speci?c action 1 mirror nibble; m[11:8] = s[8:11] 2 to 0 swap_d[2:0] w swap d selector 000 pin vpc[7:4] = vp[11:8] 001 pin vpc[3:0] = vp[11:8] 010 pin vpb[7:4] = vp[11:8] 011 pin vpb[3:0] = vp[11:8] 100* pin vpa[7:4] = vp[11:8] other pin vpa[3:0] = vp[11:8] table 26. vip_cntrl_2 register (address 22h) bit description legend: * = default value bit symbol access value description 7 mirr_e w mirror e 0* no speci?c action 1 mirror nibble; m[7:4] = s[4:7] table 24. vip_cntrl_0 register (address 20h) bit description continued legend: * = default value bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 32 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 6 to 4 swap_e[2:0] w swap e selector 000 pin vpc[7:4] = vp[7:4] 001 pin vpc[3:0] = vp[7:4] 010 pin vpb[7:4] = vp[7:4] 011 pin vpb[3:0] = vp[7:4] 100 pin vpa[7:4] = vp[7:4] 101* pin vpa[3:0] = vp[7:4] other pin vpa[3:0] = vp[7:4] 3 mirr_f w mirror f 0* no speci?c action 1 mirror nibble; m[3:0] = s[0:3] 2 to 0 swap_f[2:0] w swap f selector 000 pin vpc[7:4] = vp[3:0] 001 pin vpc[3:0] = vp[3:0] 010 pin vpb[7:4] = vp[3:0] 011 pin vpb[3:0] = vp[3:0] 100 pin vpa[7:4] = vp[3:0] 110* pin vpa[3:0] = vp[3:0] other pin vpa[3:0] = vp[3:0] table 27. vip_cntrl_3 register (address 23h) bit description legend: * = default value bit symbol access value description 7 edge w edge 0* vp-bus synchronized on positive edge of vip_clk_m 1 vp-bus synchronized on negative edge of vip_clk_m 6 x w 0* unde?ned 5 to 4 sp_sync[1:0] w sp synchronization 00 sp_cnt synchronized by hemb 01* sp_cnt synchronized by rising edge de 10 sp_cnt synchronized by rising edge of hs 11 sp_cnt ?xed at i2c_sp_cnt 3 emb w embedded 0* no speci?c action 1 use embedded synchronization codes 2 v_tgl w v_toggle 0 no speci?c action 1* toggle vs/vref table 26. vip_cntrl_2 register (address 22h) bit description continued legend: * = default value bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 33 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 1 h_tgl w h_toggle 0 no speci?c action 1* toggle hs/href 0 x_tgl w x_toggle 0* no speci?c action 1 toggle de/fref table 28. vip_cntrl_4 register (address 24h) bit description legend: * = default value bit symbol access value description 7 tst_pat w test pattern 0* no speci?c action 1 insert test pattern with high data activity 6 tst_656 w test 656 : test mode (itu656 via audio port ap) 0* no speci?c action 1 inject itu656 video via audio port 5 x w 0* unde?ned 4 ccir656 w ccir 656 : itu656 or itu656-like at the input 0* no speci?c action 1 activate itu data demultiplexing (from itu656 or itu656-like to 4 : 2 : 2 semi-planar) 3 to 2 blankit[1:0] w blankit: select source for blankit control 00* not de 01 hs and vs 10 (not hs) and vs 11 hemb and vemb 1 to 0 blc[1:0] w blanking codes 00 no insertion of blanking codes or test pattern 01* blanking codes set to rgb 4 : 4 : 4 levels 10 blanking codes set to yuv 4 : 4 : 4 levels 11 blanking codes set to yuv 4 : 2 : 2 levels table 29. vip_cntrl_5 register (address 25h) bit description legend: * = default value bit symbol access value description 7 to 3 x w 0000 0* unde?ned 2 to 1 sp_cnt[1:0] w sp counter 00* sp_cnt preset to 00 01 sp_cnt preset to 01 10 sp_cnt preset to 10 11 sp_cnt preset to 11 table 27. vip_cntrl_3 register (address 23h) bit description continued legend: * = default value bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 34 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.3.4 color space conversion registers [1] the value is a signed 11-bit twos complement integer. 0 ckcase w ckcase 0* no speci?c action 1 toggle clk1case (phase clk1 with respect to clk2) table 29. vip_cntrl_5 register (address 25h) bit description continued legend: * = default value bit symbol access value description table 30. mat_contrl register (address 80h) bit description legend: * = default value bit symbol access value description 7 to 3 x w 0000 0* unde?ned 2 mat_bp w matrix bypassed: bypasses or not the matrix and offsets 0 uses color space conversion 1* bypasses 1 and 0 mat_sc[1:0] w matrix scale factor selection: sets the scale factor to convert the ?oating matrix [c xy ] into an integer matrix [p xy ]: the choice depends on the biggest coef?cient in absolute value | c xy | 00 when 2 | c xy | < 4; s = 256 01* when 1 | c xy | < 2; s = 512 10 when | c xy | < 1; s = 1024 11 unde?ned p 11 p 12 p 13 p 21 p 22 p 23 p 31 p 32 p 33 int s c 11 c 12 c 13 c 21 c 22 c 23 c 31 c 32 c 33 () = table 31. offset input registers (address 81h to 86h) bit description legend: * = default value address register bit symbol access value description 81h mat_oi1_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 offset_in1[10:8] w 000* offset input 1: compensates the brightness value for the g/y channel [1] 82h mat_oi1_lsb 7 to 0 offset_in1[7:0] w 00h* 83h mat_oi2_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 offset_in2[10:8] w 110* offset input 2: compensates the brightness value for the r/c r channel [1] 84h mat_oi2_lsb 7 to 0 offset_in2[7:0] w 00h* 85h mat_oi3_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 offset_in3[10:8] w 110* offset input 3: compensates the brightness value for the b/c b channel [1] 86h mat_oi3_lsb 7 to 0 offset_in3[7:0] w 00h*
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 35 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] the value is a signed 11-bit twos complement integer. table 32. coef?cient registers (address 87h to 98h) bit description legend: * = default value address register bit symbol access value description 87h mat_p11_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 p11[10:8] w 010* coef?cient (1, 1): coef?cient from the g/y channel to the g/y channel [1] 88h mat_p11_lsb 7 to 0 p11[7:0] w 00h* 89h mat_p12_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 p12[10:8] w 110* coef?cient (1, 2): coef?cient from the r/c r channel to the g/y channel [1] 8ah mat_p12_lsb 7 to 0 p12[7:0] w 92h* 8bh mat_p13_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 p13[10:8] w 111* coef?cient (1, 3): coef?cient from the b/c b channel to the g/y channel [1] 8ch mat_p13_lsb 7 to 0 p13[7:0] w 50h* 8dh mat_p21_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 p21[10:8] w 010* coef?cient (2, 1): coef?cient from the g/y channel to the r/c r channel [1] 8eh mat_p21_lsb 7 to 0 p21[7:0] w 00h* 8fh mat_p22_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 p22[10:8] w 010* coef?cient (2, 2): coef?cient from the r/c r channel to the r/c r channel [1] 90h mat_p22_lsb 7 to 0 p22[7:0] w ceh* 91h mat_p23_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 p23[10:8] w 000* coef?cient (2, 3): coef?cient from the b/c b channel to the r/c r channel [1] 92h mat_p23_lsb 7 to 0 p23[7:0] w 00h* 93h mat_p31_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 p31[10:8] w 010* coef?cient (3, 1): coef?cient from the g/y channel to the b/c b channel [1] 94h mat_p31_lsb 7 to 0 p31[7:0] w 00h* 95h mat_p32_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 p32[10:8] w 000* coef?cient (3, 2): coef?cient from the r/c r channel to the b/c b channel [1] 96h mat_p32_lsb 7 to 0 p32[7:0] w 00h* 97h mat_p33_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 p33[10:8] w 011* coef?cient (3, 3): coef?cient from the b/c b channel to the b/c b channel [1] 98h mat_p33_lsb 7 to 0 p33[7:0] w 8ch* table 33. offset output registers (address 99h to 9eh) bit description legend: * = default value address register bit symbol access value description 99h mat_oo1_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 offset_out1[10:8] w 000* offset output 1: new clamp level for the g/y channel [1] 9ah mat_oo1_lsb 7 to 0 offset_out1[7:0] w 00h* 9bh mat_oo2_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 offset_out2[10:8] w 000* offset output 2: new clamp level for the r/c r channel [1] 9ch mat_oo2_lsb 7 to 0 offset_out2[7:0] w 00h*
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 36 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] the value is a signed 11-bit twos complement integer. 9.3.5 video format registers 9dh mat_oo3_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 offset_out3[10:8] w 000* offset output 3: new clamp level for the b/c b channel [1] 9eh mat_oo3_lsb 7 to 0 offset_out3[7:0] w 00h* table 33. offset output registers (address 99h to 9eh) bit description continued legend: * = default value address register bit symbol access value description table 34. vidformat register (address a0h) bit description legend: * = default value bit symbol access value description 7 to 5 x w 000* unde?ned 4 to 0 vidformat[4:0] w video format: see eia/cea-861b speci?cation 0 0000* 640 480p at 60 hz (format 1 (vga)) 0 0001 720 480p at 60 hz (format 2/3) 0 0010 1280 720p at 60 hz (format 4) 0 0011 1920 1080i at 60 hz (format 5) 0 0100 720 480i at 60 hz (format 6/7) 0 0101 720 240p at 60 hz (format 8/9) 0 0110 1920 1080p at 60 hz (format 16) 0 0111 720 576p at 50 hz (format 17/18) 0 1000 1280 720p at 50 hz (format 19) 0 1001 1920 1080i at 50 hz (format 20) 0 1010 720 576i at 50 hz (format 21/22) 0 1011 720 288p at 50 hz (format 23/24) others 1920 1080p at 50 hz (format 31) table 35. refpix_xxx, refline_xxx, npix_xxx and nline_xxx registers (address a1h to a8h) bit description legend: * = default value address register bit symbol access value description a1h refpix_msb 7 to 5 x w 000* unde?ned 4 to 0 preset_pix[12:8] w 0 0000* preset pixel: reference pixel preset a2h refpix_lsb 7 to 0 preset_pix[7:0] w 01h* a3h refline_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 preset_line[10:8] w 000* preset line: reference line preset a4h refline_lsb 7 to 0 preset_line[7:0] w 01h* a5h npix_msb 7 to 5 x w 000* unde?ned 4 to 0 npix[12:8] w 0 0000* number pixel: number of pixels per line a6h npix_lsb 7 to 0 npix[7:0] w 00h* a7h nline_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 nline[10:8] w 000* number line: number of lines per frame a8h nline_lsb 7 to 0 nline[7:0] w 00h*
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 37 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 36. vs_line_strt_xx, vs_pix_strt_xx, vs_line_end_xx, vs_pix_end_xx registers (address a9h to b8h) bit description legend: * = default value address register bit symbol access value description a9h vs_line_strt_1_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 vs_line_start_1[10:8] w 000* vertical synchronization line start 1: vertical synchronization line number for start pulse in ?eld 1 aah vs_line_strt_1_lsb 7 to 0 vs_line_start_1[7:0] w 00h* abh vs_pix_strt_1_msb 7 to 5 x w 000* unde?ned 4 to 0 vs_pix_start_1[12:8] w 0 0000* vertical synchronization pixel start 1: vertical synchronization pixel number for start pulse in ?eld 1 ach vs_pix_strt_1_lsb 7 to 0 vs_pix_start_1[7:0] w 00h* adh vs_line_end_1_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 vs_line_end_1[10:8] w 000* vertical synchronization line end 1: vertical synchronization line number for end pulse in ?eld 1 aeh vs_line_end_1_lsb 7 to 0 vs_line_end_1[7:0] w 00h* afh vs_pix_end_1_msb 7 to 5 x w 000* unde?ned 4 to 0 vs_pix_end_1[12:8] w 0 0000* vertical synchronization pixel end 1: vertical synchronization pixel number for end pulse in ?eld 1 b0h vs_pix_end_1_lsb 7 to 0 vs_pix_end_1[7:0] w 00h* b1h vs_line_strt_2_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 vs_line_start_2[10:8] w 000* vertical synchronization line start 2: vertical synchronization line number for start pulse in ?eld 2 b2h vs_line_strt_2_lsb 7 to 0 vs_line_start_2[7:0] w 00h* b3h vs_pix_strt_2_msb 7 to 5 x w 000* unde?ned 4 to 0 vs_pix_start_2[12:8] w 0 0000* vertical synchronization pixel start 2: vertical synchronization pixel number for start pulse in ?eld 2 b4h vs_pix_strt_2_lsb 7 to 0 vs_pix_start_2[7:0] w 00h* b5h vs_line_end_2_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 vs_line_end_2[10:8] w 000* vertical synchronization line end 2: vertical synchronization line number for end pulse in ?eld 2 b6h vs_line_end_2_lsb 7 to 0 vs_line_end_2[7:0] w 00h* b7h vs_pix_end_2_msb 7 to 5 x w 000* unde?ned 4 to 0 vs_pix_end_2[12:8] w 0 0000* vertical synchronization pixel end 2: vertical synchronization pixel number for end pulse in ?eld 2 b8h vs_pix_end_2_lsb 7 to 0 vs_pix_end_2[7:0] w 00h*
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 38 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 37. hs_pix_xx registers (address b9h to bch) bit description legend: * = default value address register bit symbol access value description b9h hs_pix_start_msb 7 to 5 x w 000* unde?ned 4 to 0 hs_pix_start[12:8] w 0 0000* horizontal synchronization pixel number for start pulse in ?eld 1 bah hs_pix_start_lsb 7 to 0 hs_pix_start[7:0] w 00h* bbh hs_pix_stop_msb 7 to 5 x w 000* unde?ned 4 to 0 hs_pix_end[12:8] w 0 0000* horizontal synchronization pixel number for end pulse in ?eld 2 bch hs_pix_stop_lsb 7 to 0 hs_pix_end[7:0] w 00h* table 38. vwin_start_xx and vwin_end_xx registers (address bdh and c4h) bit description legend: * = default value address register bit symbol access value description bdh vwin_start_1_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 vwin_start_1[10:8] w 000* vertical window start 1: vertical window line number for start pulse in ?eld 1 beh vwin_start_1_lsb 7 to 0 vwin_start_1[7:0] w 00h* bfh vwin_end_1_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 vwin_end_1[10:8] w 000* vertical window end 1: vertical window line number for end pulse in ?eld 1 c0h vwin_end_1_lsb 7 to 0 vwin_end_1[7:0] w 00h* c1h vwin_start_2_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 vwin_start_2[10:8] w 000* vertical window start 2: vertical window line number for start pulse in ?eld 2 c2h vwin_start_2_lsb 7 to 0 vwin_start_2[7:0] w 00h* c3h vwin_end_2_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 vwin_end_2[10:8] w 000* vertical window end 2: vertical window line number for end pulse in ?eld 2 c4h vwin_end_2_lsb 7 to 0 vwin_end_2[7:0] w 00h* table 39. de_xxx registers (address c5h to c8h) bit description legend: * = default value address register bit symbol access value description c5h de_start_msb 7 to 5 x w 000* unde?ned 4 to 0 de_start[12:8] w 0 0000* data enable start: data enable pixel number for start pulse in ?eld 1 c6h de_start_lsb 7 to 0 de_start[7:0] w 00h* c7h de_stop_msb 7 to 5 x w 000* unde?ned 4 to 0 de_end[12:8] w 0 0000* data enable end: data enable pixel number for end pulse in ?eld 2 c8h de_stop_lsb 7 to 0 de_end[7:0] w 00h* table 40. colbar_width register (address c9h) bit description legend: * = default value bit symbol access value description 7 to 0 cbw[7:0] w 00h* color bar width
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 39 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 41. tbg_cntrl_0 register (address cah) bit description legend: * = default value bit symbol access value description 7 sync_once w sync once 0* line/pixel counters are synchronized each frame 1 line/pixel counters are synchronized only once 6 sync_mthd w sync method 0* synchronization is based on combination of v and h 1 synchronization is based on combination of v and x (de) 5 frame_dis w frame disable: synchronized by linecnt = 1 and pixelcnt = 1 0* enable video frames 1 disable video frames 4 to 0 x w 0 0000* unde?ned table 42. tbg_cntrl_1 register (address cbh) bit description legend: * = default value bit symbol access value description 7 x w 0* unde?ned 6 dwin_dis w data island window disable 0* data island window active 1 data island window disabled 5 vhx_ext[2] w vhx_ext 2: bit 2 0* vs = vs_tbg (internal) 1 vs = v_vip (external) 4 vhx_ext[1] w vhx_ext 1: bit 1 0* hs = hs_tbg (internal) 1 hs = h_vip (external) 3 vhx_ext[0] w vhx_ext 0: bit 0 0* de = de_tbg (internal) 1 de = x_vip (external) 2 vh_tgl[2] w vh_tgl 2: bit 2 0* vs/hs-polarity is determined by vidformat_table 1 vs/hs-polarity depends on vh_tgl[1:0] 1 vh_tgl[1] w vh_tgl 1: bit 1 0* no speci?c action 1 toggle vs (only when vh_tgl[2] = 1) 0 vh_tgl[0] w vh_tgl 0: bit 0 0* no speci?c action 1 toggle hs (only when vh_tgl[2] = 1)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 40 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.3.6 hdmi video formatter control registers table 43. offset registers (address cch to cfh) bit description legend: * = default value address register bit symbol access value description cch vbl_offset_start 7 to 0 vbloff_start[7:0] w 00h* vertical blanking offset start: vertical blanking offset at start active window cdh vbl_offset_end 7 to 0 vbloff_end[7:0] w 00h* vertical blanking offset end: vertical blanking offset at end active window ceh hbl_offset_start 7 to 0 hbloff_start[7:0] w 00h* horizontal blanking offset start: horizontal blanking offset at start active window cfh hbl_offset_end 7 to 0 hbloff_end[7:0] w 00h* horizontal blanking offset end: horizontal blanking offset at end active window table 44. dwin_xx_de registers (address d0h and d1h) bit description legend: * = default value address register bit symbol access value description d0h dwin_re_de 7 to 0 dwin_re_de[7:0] w 11h* data window rising edge data enable: data island window rising edge offset with respect to data enable d1h dwin_fe_de 7 to 0 dwin_fe_de[7:0] w 7ah* data window falling edge data enable: data island window falling edge offset with respect to data enable table 45. hvf_cntrl_0 register (address e4h) bit description legend: * = default value bit symbol access value description 7sm w service mode 0* no speci?c action 1 service mode (color bar inserted in video path) 6 rwb w red, white, blue 0* 4-bar color bar (red - white - blue - black) 1 8-bar color bar (white - yellow - magenta - red - cyan - green - blue - black) 5 to 4 x w 00* unde?ned 3 to 2 prefil[1:0] w pre?lter 00* no pre?lter 01 [1 2 1] 10 [ - 1 0 9 16 9 0 - 1] 11 27 taps itu601-compliant halfband ?lter
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 41 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 1 to 0 intpol[1:0] w interpolation 00* bypass (from 4 :4:4 to 4:4:4) 01 intpol_by_2 (from 4:2:2 to 4:4: 4); copy sample 10 intpol_by_2 (from 4:2:2 to 4:4: 4); linear interpolation ([1 2 1] / 2 ?lter) 11 unde?ned table 46. hvf_cntrl_1 register (address e5h) bit description legend: * = default value bit symbol access value description 7 x w 0* unde?ned 6 semi_planar w semi-planar 0 4 : 4 : 4 at the input of the vrf-module 1 4 : 2 : 2 at the input of the vrf-module 5 to 4 pad[1:0] w pad 00* 12-bit data path 01 8-bit data path; 4 lsbs set to 0000 10 10-bit data path; 2 lsbs set to 00 11 10-bit data path; 2 lsbs set to 00 3 to 2 vqr[1:0] w video quantization range 00* full-scale 01 rgb/yuv (max. 235 to min. 16) 10 y (max. 235 to min. 16); u (max. 240 to min. 16); v (max. 240 to min. 16) 11 y (max. 235 to min. 16); u (max. 240 to min. 16); v (max. 240 to min. 16) 1 yuvblk w yuv blank 0* uv blank level = 16 1 uv blank level = 0 0 for w formatter 0* transparent formatter (4 : 4 : 4 or 4 :2:2 unprocessed) 1 4 : 2 : 2 output format (4 : 4 : 4 to 4:2:2 conversion active) table 45. hvf_cntrl_0 register (address e4h) bit description continued legend: * = default value bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 42 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.3.7 timer control registers 9.3.8 ndiv register 9.3.9 control registers table 47. timer control registers (address e8h to eah) bit description legend: * = default value address register bit symbol access value description e8h timer_h 7 im_clksel w im timer clock select 0 ddc_master clocked by hdmi_clk / (ndiv_im[3:0] + 1) 1 ddc_master clocked by cclk / 3 (typically 10 mhz) 6 wd_clksel w watchdog timer clock select 0 wd_timer clocked by hdmi_clk / (ndiv_pf[7:0] + 1) 1 wd_timer clocked by cclk / 32 5 to 2 x w 0000* unde?ned 1 to 0 tim_h[1:0] w timer control register height 00 tim[17:16] = 00 01* tim[17:16] = 01 10 tim[17:16] = 10 00 tim[17:16] = 11 e9h timer_m 7 to 0 tim_m[7:0] w timer control register medium c2h* tim[15:8] = tim_m[7:0] eah timer_l 7 to 0 tim_l[7:0] w timer control register low 40h* tim[7:0] = tim_l[7:0] table 48. ndiv_xxx registers (address eeh and efh) bit description legend: * = default value address register bit symbol access value description eeh ndiv_im 7 to 4 x w 0000* unde?ned 3 to 0 ndiv_im[3:0] w n divisor ddc-bus master 0011* n divisor to set clock period for ddc-bus master efh ndiv_pf 7 to 0 ndiv_pf[7:0] w n divisor pixel frequency 1bh* n divisor to set clock period for timers (equals pixel frequency) table 49. control registers (address f0h to f2h, f9h, fdh and feh) bit description legend: * = default value address register bit symbol access value description f0h rpt_cntrl 7 to 4 x w 0000* unde?ned 3 to 0 repeat[3:0] w 0000* repeat: repeater control f1h lead_off 7 to 4 x w 0000* unde?ned 3 to 0 lead_offset[3:0] w 0010* leading offset: leading offset for dwin (in case rpt > 1)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 43 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.3.10 current page address register 9.4 scaler page register de?nitions the current page address for the scaler page is 01h. the con?guration of the registers for this page is given in t ab le 51 . f2h trail_off 7 to 4 x w 0000* unde?ned 3 to 0 trail_offset[3:0] w 0010* trailing offset: trailing offset for dwin (in case rpt > 1) f9h ghost_xaddr 7 to 1 ghost_xaddr[6:0] w 0110 000* ghost extended address 0 a0_zero w 0* - fdh aip_clksel 7 to 5 x w 000* unde?ned 4 to 3 sel_aip[1:0] w selection audio input 00* s/pdif 01 i 2 s-bus 1x for internal use 2 sel_pol_clk w 0* select polarity clock: for internal use 1 to 0 sel_fs[1:0] w select fs: cts reference 00* aclk 01 mclk 1x fs_64 (s/pdif) feh ghost_addr 7 to 1 ghost_addr[6:0] w 1010 000* ghost address 0 ghost_dis w 1* - table 49. control registers (address f0h to f2h, f9h, fdh and feh) bit description continued legend: * = default value address register bit symbol access value description table 50. curpage_adr register (address ffh) bit description legend: * = default value bit symbol access value description 7 to 0 curpage_adr[7:0] w 00h* current page address: selects the current memory page
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 44 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 51. i 2 c-bus registers of memory page 01h [1] register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb) sc_vidformat 00h w lut_sel[1:0] vid_format_o[2:0] vid_format_i[2:0] 0000 0000 sc_cntrl 01h w x x x x il_out_ on phases_ v vs_on deil_on 0000 0000 sc_delta_phase_v 02h w x delta_phase_v[6:0] 0001 1110 sc_delta_phase_h 03h w x x x delta_phase_h[4:0] 0001 0000 sc_start_phase_h 04h w x x x x start_phase_h[3:0] 0000 0000 sc_npix_in_lsb 05h w npix_in[7:0] 1101 0000 sc_npix_in_msb 06h w x xxxxx npix_in[9:8] 0000 0010 sc_npix_out_lsb 07h w npix_out[7:0] 1101 0000 sc_npix_out_msb 08h w x xxxx npix_out[10:8] 0000 0010 sc_nline_in_lsb 09h w nline_in[7:0] 0100 0000 sc_nline_in_msb 0ah w x xxxxx nline_in[9:8] 0000 0010 sc_nline_out_lsb 0bh w nline_out[7:0] 0100 0000 sc_nline_out_msb 0ch w x xxxxx nline_out[9:8] 0000 0010 sc_nline_skip 0dh w x xxxx nline_skip[2:0] 0000 0000 sc_sample_buffill 0eh r sample_buffill_command[7:0] xxxx xxxx sc_max_buffill_p_0 0fh r max_buffill_p[7:0] xxxx xxxx sc_max_buffill_p_1 10h r x x x x max_buffill_p[11:8] xxxx xxxx sc_max_buffill_d_0 11h r max_buffill_d[7:0] xxxx xxxx sc_max_buffill_d_1 12h r x x x x max_buffill_d[11:8] xxxx xxxx sc_sample_fifofill 13h r sample_fifofill_command[7:0] xxxx xxxx sc_max_fifofill_pi 14h r x x x max_fifofill_pi[4:0] xxxx xxxx sc_min_fifofill_po1 15h r x x x min_fifofill_po1[4:0] xxxx xxxx sc_min_fifofill_po2 16h r x x x min_fifofill_po2[4:0] xxxx xxxx sc_min_fifofill_po3 17h r x x x min_fifofill_po3[4:0] xxxx xxxx sc_min_fifofill_po4 18h r x x x min_fifofill_po4[4:0] xxxx xxxx sc_max_fifofill_di 19h r x x x max_fifofill_di[4:0] xxxx xxxx sc_max_fifofill_do 1ah r x x x max_fifofill_do[4:0] xxxx xxxx sc_vs_lut_0 1bh w vs_lut0[7:0] xxxx xxxx sc_vs_lut_1 1ch w vs_lut1[7:0] xxxx xxxx sc_vs_lut_2 1dh w vs_lut2[7:0] xxxx xxxx sc_vs_lut_3 1eh w vs_lut3[7:0] xxxx xxxx
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 45 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter sc_vs_lut_4 1fh w vs_lut4[7:0] xxxx xxxx sc_vs_lut_5 20h w vs_lut5[7:0] xxxx xxxx sc_vs_lut_6 21h w vs_lut6[7:0] xxxx xxxx sc_vs_lut_7 22h w vs_lut7[7:0] xxxx xxxx sc_vs_lut_8 23h w vs_lut8[7:0] xxxx xxxx sc_vs_lut_9 24h w vs_lut9[7:0] xxxx xxxx sc_vs_lut_10 25h w vs_lut10[7:0] xxxx xxxx sc_vs_lut_11 26h w vs_lut11[7:0] xxxx xxxx sc_vs_lut_12 27h w vs_lut12[7:0] xxxx xxxx sc_vs_lut_13 28h w vs_lut13[7:0] xxxx xxxx sc_vs_lut_14 29h w vs_lut14[7:0] xxxx xxxx sc_vs_lut_15 2ah w vs_lut15[7:0] xxxx xxxx sc_vs_lut_16 2bh w vs_lut16[7:0] xxxx xxxx sc_vs_lut_17 2ch w vs_lut17[7:0] xxxx xxxx sc_vs_lut_18 2dh w vs_lut18[7:0] xxxx xxxx sc_vs_lut_19 2eh w vs_lut19[7:0] xxxx xxxx sc_vs_lut_20 2fh w vs_lut20[7:0] xxxx xxxx sc_vs_lut_21 30h w vs_lut21[7:0] xxxx xxxx sc_vs_lut_22 31h w vs_lut22[7:0] xxxx xxxx sc_vs_lut_23 32h w vs_lut23[7:0] xxxx xxxx sc_vs_lut_24 33h w vs_lut24[7:0] xxxx xxxx sc_vs_lut_25 34h w vs_lut25[7:0] xxxx xxxx sc_vs_lut_26 35h w vs_lut26[7:0] xxxx xxxx sc_vs_lut_27 36h w vs_lut27[7:0] xxxx xxxx sc_vs_lut_28 37h w vs_lut28[7:0] xxxx xxxx sc_vs_lut_29 38h w vs_lut29[7:0] xxxx xxxx sc_vs_lut_30 39h w vs_lut30[7:0] xxxx xxxx sc_vs_lut_31 3ah w vs_lut31[7:0] xxxx xxxx sc_vs_lut_32 3bh w vs_lut32[7:0] xxxx xxxx sc_vs_lut_33 3ch w vs_lut33[7:0] xxxx xxxx sc_vs_lut_34 3dh w vs_lut34[7:0] xxxx xxxx sc_vs_lut_35 3eh w vs_lut35[7:0] xxxx xxxx table 51. i 2 c-bus registers of memory page 01h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 46 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter sc_vs_lut_36 3fh w vs_lut36[7:0] xxxx xxxx sc_vs_lut_37 40h w vs_lut37[7:0] xxxx xxxx sc_vs_lut_38 41h w vs_lut38[7:0] xxxx xxxx sc_vs_lut_39 42h w vs_lut39[7:0] xxxx xxxx sc_vs_lut_40 43h w vs_lut40[7:0] xxxx xxxx sc_vs_lut_41 44h w vs_lut41[7:0] xxxx xxxx sc_vs_lut_42 45h w vs_lut42[7:0] xxxx xxxx sc_vs_lut_43 46h w vs_lut43[7:0] xxxx xxxx sc_vs_lut_44 47h w vs_lut44[7:0] xxxx xxxx not used 48h - - 0000 0000 ::: : : not used 9fh - - 0000 0000 vidformat a0h w x xxxx vidformat[2:0] 0000 0000 refpix_msb a1h w x xxxxx preset_pix[9:8] 0000 0000 refpix_lsb a2h w preset_pix[7:0] 0000 0001 refline_msb a3h w x xxxxx preset_line[9:8] 0000 0000 refline_lsb a4h w preset_line[7:0] 0000 0001 npix_msb a5h w x xxxxx npix[9:8] 0000 0000 npix_lsb a6h w npix[7:0] 0000 0000 nline_msb a7h w x xxxxx nline[9:8] 0000 0000 nline_lsb a8h w nline[7:0] 0000 0000 not used a9h - - 0000 0000 ::: : : not used bch - - 0000 0000 vwin_start_1_msb bdh w x xxxxx vwin_start_1[9:8] 0000 0000 vwin_start_1_lsb beh w vwin_start_1[7:0] 0000 0000 vwin_end_1_msb bfh w x xxxxx vwin_end_1[9:8] 0000 0000 vwin_end_1_lsb c0h w vwin_end_1[7:0] 0000 0000 vwin_start_2_msb c1h w x xxxxx vwin_start_2[9:8] 0000 0000 vwin_start_2_lsb c2h w vwin_start_2[7:0] 0000 0000 vwin_end_2_msb c3h w x xxxxx vwin_end_2[9:8] 0000 0000 vwin_end_2_lsb c4h w vwin_end_2[7:0] 0000 0000 table 51. i 2 c-bus registers of memory page 01h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 47 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] r: reading register w: writing register x: bit must be set to default value for proper operation -: not used de_start_msb c5h w x xxxxx de_start[9:8] 0000 0000 de_start_lsb c6h w de_start[7:0] 0000 0000 de_stop_msb c7h w x xxxxx de_end[9:8] 0000 0000 de_stop_lsb c8h w de_end[7:0] 0000 0000 not used c9h - -------- 0000 0000 tbg_cntrl_0 cah w sync_ once sync_ mthd frame_ dis x top_ext de_ext top_sel top_tgl 0000 0000 not used cbh - - 0000 0000 ::: : : not used feh - - 0000 0000 curpage_adr ffh w curpage_adr[7:0] 0000 0000 table 51. i 2 c-bus registers of memory page 01h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 48 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.4.1 scaler control registers table 52. sc_vidformat register (address 00h) bit description legend: * = default value bit symbol access value description 7 and 6 lut_sel[1:0] w look-up table select 00* default coef?cient set #1 (video) 01 default coef?cient set #2 (enhanced sharpness) 1x coef?cient set as programmed via i 2 c-bus 5 to 3 vid_format_o[2:0] w video format output 000* 480p 60 hz 001 576p 50 hz 010 720p 50 hz/60 hz 011 1080i 50 hz/60 hz 1xx customized format 2 to 0 vid_format_i[2:0] w video format input 000* 480i 60 hz 001 576i 50 hz 010 480p 60 hz 011 576p 50 hz 1xx customized format table 53. sc_cntrl register (address 01h) bit description legend: * = default value bit symbol access value description 7 to 4 x w 0000* unde?ned 3 il_out_on w interlaced output on 0* internal line phase toggle is ignored 1 interlaced output; output lines depend on internal line phase toggle 2 phases_v w vertical phases 0* 90 vertical phases 1 54 vertical phases 1 vs_on w vertical scaler on 0* vertical scaler off 1 vertical scaler on 0 deil_on w deinterlacer on 0* deinterlacer off 1 deinterlacer on
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 49 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 54. sc_x_phase_x registers (address 02h to 04h) bit description legend: * = default value address register bit symbol access value description 02h sc_delta_phase_v 7 x w 0* unde?ned 6 to 0 delta_phase_v[6:0] w 001 1110* delta phase vertical 03h sc_delta_phase_h 7 to 5 x w 000* unde?ned 4 to 0 delta_phase_h[4:0] w 1 0000* delta phase horizonta l 04h sc_start_phase_h 7 to 4 x w 0000* unde?ned 3 to 0 start_phase_h[3:0] w 0000* start phase horizontal table 55. sc_npix_xx registers (address 05h to 08h) bit description legend: * = default value address register bit symbol access value description 06h sc_npix_in_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 npix_in[9:8] w 10* number of input pixels 05h sc_npix_in_lsb 7 to 0 npix_in[7:0] w d0h* 08h sc_npix_out_msb 7 to 3 x w 0000 0* unde?ned 2 to 0 npix_out[10:8] w 010* number of output pixels 07h sc_npix_out_lsb 7 to 0 npix_out[7:0] w d0h* table 56. sc_nline_xx registers (address 09h to 0dh) bit description legend: * = default value address register bit symbol access value description 0ah sc_nline_in_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 nline_in[9:8] w 10* number of input lines 09h sc_nline_in_lsb 7 to 0 nline_in[7:0] w 40h* 0ch sc_nline_out_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 nline_out[9:8] w 10* number of output lines 0bh sc_nline_out_lsb 7 to 0 nline_out[7:0] w 40h* 0dh sc_nline_skip 7 to 3 x w 0000 0* unde?ned 2 to 0 nline_skip[2:0] w 000* number of output lines skipped : by vertical scaler table 57. sc_x_buffill_xx registers (address 0eh to 12h) bit description legend: * = default value address register bit symbol access value description 0eh sc_sample_buffill 7 to 0 sample_buffill_ command[7:0] r- sample buffer ?lling command: when this address is read the buffill values are sampled 10h sc_max_buffill_p_1 7 to 4 x r - unde?ned 3 to 0 max_buffill_p[11:8] r - max buffer ?lling primary: ?lling primary video buffer 0fh sc_max_buffill_p_0 7 to 0 max_buffill_p[7:0] r -
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 50 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 12h sc_max_buffill_d_1 7 to 4 x r - unde?ned 3 to 0 max_buffill_d[11:8] r - max buffer ?lling deinterlaced : ?lling video deinterlaced buffer 11h sc_max_buffill_d_0 7 to 0 max_buffill_d[7:0] r - table 57. sc_x_buffill_xx registers (address 0eh to 12h) bit description continued legend: * = default value address register bit symbol access value description table 58. sc_xx_fifofill_xx registers (address 13h to 1ah) bit description legend: * = default value address register bit symbol access value description 13h sc_sample_fifofill 7 to 0 sample_fifofill_ command[7:0] r- sample fifo ?lling command: when this address is read the fifofill values are sampled 14h sc_max_fifofill_pi 7 to 5 x r - unde?ned 4 to 0 max_fifofill_pi[4:0] r - max fifo ?lling primary input: ?lling primary video input fifo 15h sc_min_fifofill_po1 7 to 5 x r - unde?ned 4 to 0 min_fifofill_po1[4:0] r - min fifo ?lling primary output 1 : ?lling primary video output fifo#1 16h sc_min_fifofill_po2 7 to 5 x r - unde?ned 4 to 0 min_fifofill_po2[4:0] r - min fifo ?lling primary output 2 : ?lling primary video output fifo#2 17h sc_min_fifofill_po3 7 to 5 x r - unde?ned 4 to 0 min_fifofill_po3[4:0] r - min fifo ?lling primary output 3 : ?lling primary video output fifo#3 18h sc_min_fifofill_po4 7 to 5 x r - unde?ned 4 to 0 min_fifofill_po4[4:0] r - min fifo ?lling primary output 4 : ?lling primary video output fifo#4 19h sc_max_fifofill_di 7 to 5 x r - unde?ned 4 to 0 max_fifofill_di[4:0] r - max fifo ?lling deinterlaced input : ?lling deinterlaced video input fifo 1ah sc_max_fifofill_do 7 to 5 x r - unde?ned 4 to 0 max_fifofill_do[4:0] r - max fifo ?lling deinterlaced output : ?lling deinterlaced video output fifo
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 51 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 59. sc_vs_lut_xx registers (address 1bh to 47h) bit description legend: * = default value address register bit symbol access value description 1bh sc_vs_lut_0 7 to 0 vs_lut0[7:0] w - vertical scaler lut 0: external lut coef?cient[0] for vertical scaler 1ch sc_vs_lut_1 7 to 0 vs_lut1[7:0] w - vertical scaler lut 1: external lut coef?cient[1] for vertical scaler 1dh sc_vs_lut_2 7 to 0 vs_lut2[7:0] w - vertical scaler lut 2: external lut coef?cient[2] for vertical scaler 1eh sc_vs_lut_3 7 to 0 vs_lut3[7:0] w - vertical scaler lut 3: external lut coef?cient[3] for vertical scaler 1fh sc_vs_lut_4 7 to 0 vs_lut4[7:0] w - vertical scaler lut 4: external lut coef?cient[4] for vertical scaler 20h sc_vs_lut_5 7 to 0 vs_lut5[7:0] w - vertical scaler lut 5: external lut coef?cient[5] for vertical scaler 21h sc_vs_lut_6 7 to 0 vs_lut6[7:0] w - vertical scaler lut 6: external lut coef?cient[6] for vertical scaler 22h sc_vs_lut_7 7 to 0 vs_lut7[7:0] w - vertical scaler lut 7: external lut coef?cient[7] for vertical scaler 23h sc_vs_lut_8 7 to 0 vs_lut8[7:0] w - vertical scaler lut 8: external lut coef?cient[8] for vertical scaler 24h sc_vs_lut_9 7 to 0 vs_lut9[7:0] w - vertical scaler lut 9: external lut coef?cient[9] for vertical scaler 25h sc_vs_lut_10 7 to 0 vs_lut10[7:0] w - vertical scaler lut 10: external lut coef?cient[10] for vertical scaler 26h sc_vs_lut_11 7 to 0 vs_lut11[7:0] w - vertical scaler lut 11: external lut coef?cient[11] for vertical scaler 27h sc_vs_lut_12 7 to 0 vs_lut12[7:0] w - vertical scaler lut 12: external lut coef?cient[12] for vertical scaler 28h sc_vs_lut_13 7 to 0 vs_lut13[7:0] w - vertical scaler lut 13: external lut coef?cient[13] for vertical scaler 29h sc_vs_lut_14 7 to 0 vs_lut14[7:0] w - vertical scaler lut 14: external lut coef?cient[14] for vertical scaler 2ah sc_vs_lut_15 7 to 0 vs_lut15[7:0] w - vertical scaler lut 15: external lut coef?cient[15] for vertical scaler 2bh sc_vs_lut_16 7 to 0 vs_lut16[7:0] w - vertical scaler lut 16: external lut coef?cient[16] for vertical scaler 2ch sc_vs_lut_17 7 to 0 vs_lut17[7:0] w - vertical scaler lut 17: external lut coef?cient[17] for vertical scaler 2dh sc_vs_lut_18 7 to 0 vs_lut18[7:0] w - vertical scaler lut 18: external lut coef?cient[18] for vertical scaler 2eh sc_vs_lut_19 7 to 0 vs_lut19[7:0] w - vertical scaler lut 19: external lut coef?cient[19] for vertical scaler 2fh sc_vs_lut_20 7 to 0 vs_lut20[7:0] w - vertical scaler lut 20: external lut coef?cient[20] for vertical scaler 30h sc_vs_lut_21 7 to 0 vs_lut21[7:0] w - vertical scaler lut 21: external lut coef?cient[21] for vertical scaler 31h sc_vs_lut_22 7 to 0 vs_lut22[7:0] w - vertical scaler lut 22: external lut coef?cient[22] for vertical scaler
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 52 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 32h sc_vs_lut_23 7 to 0 vs_lut23[7:0] w - vertical scaler lut 23: external lut coef?cient[23] for vertical scaler 33h sc_vs_lut_24 7 to 0 vs_lut24[7:0] w - vertical scaler lut 24: external lut coef?cient[24] for vertical scaler 34h sc_vs_lut_25 7 to 0 vs_lut25[7:0] w - vertical scaler lut 25: external lut coef?cient[25] for vertical scaler 35h sc_vs_lut_26 7 to 0 vs_lut26[7:0] w - vertical scaler lut 26: external lut coef?cient[26] for vertical scaler 36h sc_vs_lut_27 7 to 0 vs_lut27[7:0] w - vertical scaler lut 27: external lut coef?cient[27] for vertical scaler 37h sc_vs_lut_28 7 to 0 vs_lut28[7:0] w - vertical scaler lut 28: external lut coef?cient[28] for vertical scaler 38h sc_vs_lut_29 7 to 0 vs_lut29[7:0] w - vertical scaler lut 29: external lut coef?cient[29] for vertical scaler 39h sc_vs_lut_30 7 to 0 vs_lut30[7:0] w - vertical scaler lut 30: external lut coef?cient[30] for vertical scaler 3ah sc_vs_lut_31 7 to 0 vs_lut31[7:0] w - vertical scaler lut 31: external lut coef?cient[31] for vertical scaler 3bh sc_vs_lut_32 7 to 0 vs_lut32[7:0] w - vertical scaler lut 32: external lut coef?cient[32] for vertical scaler 3ch sc_vs_lut_33 7 to 0 vs_lut33[7:0] w - vertical scaler lut 33: external lut coef?cient[33] for vertical scaler 3dh sc_vs_lut_34 7 to 0 vs_lut34[7:0] w - vertical scaler lut 34: external lut coef?cient[34] for vertical scaler 3eh sc_vs_lut_35 7 to 0 vs_lut35[7:0] w - vertical scaler lut 35: external lut coef?cient[35] for vertical scaler 3fh sc_vs_lut_36 7 to 0 vs_lut36[7:0] w - vertical scaler lut 36: external lut coef?cient[36] for vertical scaler 40h sc_vs_lut_37 7 to 0 vs_lut37[7:0] w - vertical scaler lut 37: external lut coef?cient[37] for vertical scaler 41h sc_vs_lut_38 7 to 0 vs_lut38[7:0] w - vertical scaler lut 38: external lut coef?cient[38] for vertical scaler 42h sc_vs_lut_39 7 to 0 vs_lut39[7:0] w - vertical scaler lut 39: external lut coef?cient[39] for vertical scaler 43h sc_vs_lut_40 7 to 0 vs_lut40[7:0] w - vertical scaler lut 40: external lut coef?cient[40] for vertical scaler 44h sc_vs_lut_41 7 to 0 vs_lut41[7:0] w - vertical scaler lut 41: external lut coef?cient[41] for vertical scaler 45h sc_vs_lut_42 7 to 0 vs_lut42[7:0] w - vertical scaler lut 42: external lut coef?cient[42] for vertical scaler 46h sc_vs_lut_43 7 to 0 vs_lut43[7:0] w - vertical scaler lut 43: external lut coef?cient[43] for vertical scaler 47h sc_vs_lut_44 7 to 0 vs_lut44[7:0] w - vertical scaler lut 44: external lut coef?cient[44] for vertical scaler table 59. sc_vs_lut_xx registers (address 1bh to 47h) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 53 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.4.2 scaling input time base generator control registers table 60. vidformat register (address a0h) bit description legend: * = default value bit symbol access value description 7 to 3 x w 0000 0* unde?ned 2 to 0 vidformat[2:0] w video format: time base generator for scaler input formats 000* 480i 60 hz 001 576i 50 hz 010 480p 60 hz 011 576p 50 hz 1xx reserved for future use table 61. refpix_xx, refline_xx, npix_xx and nline_xx registers (address a1h to a8h) bit description legend: * = default value address register bit symbol access value description a1h refpix_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 preset_pix[9:8] w 00* preset pixel: reference pixel preset a2h refpix_lsb 7 to 0 preset_pix[7:0] w 01h* a3h refline_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 preset_line[9:8] w 00* preset line: reference line preset a4h refline_lsb 7 to 0 preset_line[7:0] w 01h* a5h npix_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 npix[9:8] w 00* number pixel: number of pixels per line a6h npix_lsb 7 to 0 npix[7:0] w 00h* a7h nline_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 nline[9:8] w 00* number line: number of lines per frame a8h nline_lsb 7 to 0 nline[7:0] w 00h* table 62. vwin_start_x_xx and vwin_end_x_xx registers (address bdh to c4h) bit description legend: * = default value address register bit symbol access value description bdh vwin_start_1_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 vwin_start_1[9:8] w 00* vertical window start 1: vertical window line number for start pulse in ?eld 1 beh vwin_start_1_lsb 7 to 0 vwin_start_1[7:0] w 00h* bfh vwin_end_1_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 vwin_end_1[9:8] w 00* vertical window end 1 : vertical window line number for end pulse in ?eld 1 c0h vwin_end_1_lsb 7 to 0 vwin_end_1[7:0] w 00h* c1h vwin_start_2_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 vwin_start_2[9:8] w 00* vertical window start 2 : vertical window line number for start pulse in ?eld 2 c2h vwin_start_2_lsb 7 to 0 vwin_start_2[7:0] w 00h*
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 54 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter c3h vwin_end_2_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 vwin_end_2[9:8] w 00* vertical window end 2 : vertical window line number for end pulse in ?eld 2 c4h vwin_end_2_lsb 7 to 0 vwin_end_2[7:0] w 00h* table 62. vwin_start_x_xx and vwin_end_x_xx registers (address bdh to c4h) bit description continued legend: * = default value address register bit symbol access value description table 63. de_start_x and de_stop_x registers (address c5h to c8h) bit description legend: * = default value address register bit symbol access value description c5h de_start_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 de_start[9:8] w 00* data enable start : data enable pixel number for start pulse in ?eld 1 c6h de_start_lsb 7 to 0 de_start[7:0] w 00h* c7h de_stop_msb 7 to 2 x w 0000 00* unde?ned 1 to 0 de_end[9:8] w 00* data enable end : data enable pixel number for end pulse in ?eld 2 c8h de_stop_lsb 7 to 0 de_end[7:0] w 00h* table 64. tbg_cntrl_0 register (address cah) bit description legend: * = default value bit symbol access value description 7 sync_once w sync once 0* line/pixel counters are synchronized each frame 1 line/pixel counters are synchronized only once 6 sync_mthd w sync method 0* synchronization is based on combination of v and h 1 synchronization is based on combination of v and x (de) 5 frame_dis w frame disable : synchronized by linecnt = 1 and pixelcnt = 1 0* enable video frames 1 disable video frames 4 x w 0* unde?ned 3 top_ext w top external 0* top = top_tbg_sci 1 top = x_vip (external; fref) 2 de_ext w data enable external 0* de = de_tbg_sci (internal) 1 de = x_vip (external; de)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 55 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.4.3 current page address register 9.5 pll settings page register de?nitions the current page address for the pll settings page is 02h. the con?guration of the registers for this page is given in t ab le 66 . 1 top_sel w top select 0* top_tbg_sci = top_tbg_sci (internal; programmed via i 2 c-bus) 1 top_tbg_sci = top_tbg_vrf 0 top_tgl w top toggle 0* no speci?c action 1 toggle top_tbg_sci table 64. tbg_cntrl_0 register (address cah) bit description continued legend: * = default value bit symbol access value description table 65. curpage_adr register (address ffh) bit description legend: * = default value bit symbol access value description 7 to 0 curpage_adr[7:0] w 00h* current page address: selects the current memory page
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 56 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] r: reading register w: writing register x: bit must be set to default value for proper operation -: not used table 66. i 2 c-bus registers of memory page 02h [1] register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb) pll_serial_1 00h r/w x srl_man_ip srl_reg_ip[2:0] srl_iz[1:0] srl_fdn 0000 0000 pll_serial_2 01h r/w srl_pr[3:0] x x srl_nosc[1:0] 0000 0000 pll_serial_3 02h r/w x x x srl_pxin_ sel x x srl_de srl_ccir 0000 0000 serializer 03h r/w srl_phase3[3:0] srl_phase2[3:0] 0000 0000 buffer_out 04h r/w x x x x srl_force[1:0] srl_clk[1:0] 0000 0000 pll_scg1 05h r/w x x x x x x x scg_fdn 0000 0001 pll_scg2 06h r/w bypass_ scg x x selpllcl kin x x scg_nosc[1:0] 1001 0000 pll_scgn1 07h r/w scg_ndiv[7:0] 1111 1010 pll_scgn2 08h r/w x x x x x scg_ndiv[10:8] 0000 0000 pll_scgr1 09h r/w scg_rdiv[7:0] 0101 1011 pll_scgr2 0ah r/w x x x x x x x scg_ rdiv[8] 0000 0000 pll_de 0bh r/w bypass_ pllde x pllde_nosc[1:0] x pllde_iz[1:0] pllde_ fdn 1000 0001 ccir_div 0ch r/w x x x x x x x refdiv2 0000 0001 vai_pll 0dh r x pllde_hvp pllscg_ hvp pllsrl_ hvp x pllde_ lock pllscg_ lock pllsrl_ lock 0000 0000 audio_div 0eh r/w x x x x x audio_div[2:0] 0000 0011 test1 0fh r/w x x x tstser phoe x x tst_nosc tst_hvp 0000 0000 test2 10h r/w x x x x x x pwd1v8 divtestoe 0000 0000 sel_clk 11h r/w x x x x ena_sc_ clk sel_vrf_clk[1:0] sel_clk1 0000 0000 not used 12h - - 0000 0000 ::: : : not used feh - - 0000 0000 curpage_adr ffh w curpage_adr[7:0] 0000 0000
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 57 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.5.1 pll serial registers table 67. pll_serial_1 register (address 00h) bit description legend: * = default value bit symbol access value description 7 x r/w 0* unde?ned 6 srl_man_ip r/w serializer manual current pole 0* automatic setting of output current pole charge pump (ip_auto) 1 manual setting of output current pole charge pump (ip_manual) 5 to 3 srl_reg_ip[2:0] r/w serializer current pole: pll pole charge pump output current (ip_manual) 000* 400 na 001 200 na 010 133 na 011 100 na 100 80 na 101 66 na 110 57 na 111 50 na 2 to 1 srl_iz[1:0] r/w serializer zero current : pll zero charge pump output current 00* iz / 5 01 iz / 10 10 iz / 15 11 iz / 20 0 srl_fdn r/w serializer fdn 0* normal (pll loop active) 1 standby (pll loop open)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 58 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 68. pll_serial_2 register (address 01h) bit description legend: * = default value bit symbol access value description 7 to 4 srl_pr[3:0] r/w serializer pixel repetition: pixel repetition factor (ip_auto) 0000* pr = 1 (ip_auto = 400 na) 0001 pr = 2 (ip_auto = 200 na) 0010 pr = 3 (ip_auto = 133 na) 0011 pr = 4 (ip_auto = 100 na) 0100 pr = 5 (ip_auto = 80 na) 0101 pr = 6 (ip_auto = 66 na) 0110 pr = 7 (ip_auto = 57 na) 0111 pr = 8 (ip_auto = 50 na) 1000 pr = 9 (ip_auto = 50 na) 1001 pr = 10 (ip_auto = 50 na) other unde?ned 3 to 2 x r/w 00* unde?ned 1 to 0 srl_nosc[1:0] r/w serializer n oscillator : predivider division factor 00* div_by_1; pll output frequency range = (800 to 1500) msample/s (iz = 1.0+) 01 div_by_2; pll output frequency range = (400 to 800) msample/s (iz = 1.5+) 10 div_by_4; pll output frequency range = (200 to 400) msample/s (iz = 2.0+) 11 div_by_4; pll output frequency range = (200 to 400) msample/s (iz = 2.0+) table 69. pll_serial_3 register (address 02h) bit description legend: * = default value bit symbol access value description 7 to 5 x r/w 000* unde?ned 4 srl_pxin_sel r/w serializer pixel input select 0* pxinclko = scaclko 1 pxinclko = scaclko / 2 3 to 2 x r/w 00* unde?ned 1 srl_de r/w serializer double edge : double edge divider in feedback loop 0* no division 1 divide by 2 0 srl_ccir r/w serializer ccir 0* pllsrl_in = pllsrl_re?n 1 pllsrl_in = pllsrl_re?n / 2
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 59 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 70. serializer register (address 03h) bit description legend: * = default value bit symbol access value description 7 to 4 srl_phase3[3:0] r/w 0000* serializer phase 3 : phase selection of third storage level of the serializer input 3 to 0 srl_phase2[3:0] r/w 0000* serializer phase 2 : phase selection of second storage level of the serializer input table 71. buffer_out register (address 04h) bit description legend: * = default value bit symbol access value description 7 to 4 x r/w 0000* unde?ned 3 to 2 srl_force[1:0] r/w serializer force 00* tmds outputs active (normal operation) 01 tmds outputs active (normal operation) 10 tmds outputs forced '0' 11 tmds outputs forced '1' 1 to 0 srl_clk[1:0] r/w serializer clock 00* tmds txc = tmdsclk (normal operation) 01 tmds txc = serclk / 2 10 tmds txc = unde?ned 11 tmds txc = serclk table 72. pll_scg1 register (address 05h) bit description legend: * = default value bit symbol access value description 7 to 1 x r/w 0000 000* unde?ned 0 scg_fdn r/w scg fnd 0 normal (pll loop active) 1* standby (pll loop open) table 73. pll_scg2 register (address 06h) bit description legend: * = default value bit symbol access value description 7 bypass_scg r/w bypass scg 0 scaclko = scg_nosc predivider output 1* scaclko = pllscg_inref 6 to 5 x r/w 00* unde?ned 4 selpllclkin r/w select pll clock input 0 pllscg_in = pllsca_inref 1* pllscg_in = pllclkin 3 to 2 x r/w 00* unde?ned
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 60 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 1 to 0 scg_nosc[1:0] r/w scg n oscillator 00* div_by_1; pll output frequency range = (80 to 150) msample/s 01 div_by_2; pll output frequency range = (40 to 80) msample/s 10 div_by_4; pll output frequency range = (20 to 40) msample/s 11 div_by_8; pll output frequency range = (10 to 20) msample/s table 73. pll_scg2 register (address 06h) bit description continued legend: * = default value bit symbol access value description table 74. pll_scgnx registers (address 07h to 08h) bit description legend: * = default value address register bit symbol access value description 08h pll_scgn2 7 to 3 x r/w 0000 0* unde?ned 2 to 0 scg_ndiv[10:8] r/w 000* scg n divider : pll feedback oscillator divider 07h pll_scgn1 7 to 0 scg_ndiv[7:0] r/w fah* table 75. pll_scgrx registers (address 09h to 0ah) bit description legend: * = default value address register bit symbol access value description 0ah pll_scgr2 7 to 1 x r/w 0000 000* unde?ned 0 scg_rdiv[8] r/w 0* scg r divider : divider value of the pll reference input clock 09h pll_scgr1 7 to 0 scg_rdiv[7:0] r/w 5bh* table 76. pll_de register (address 0bh) bit description legend: * = default value bit symbol access value description 7 bypass_pllde r/w bypass pll double edge 0 pllde0 = de_nosc predivider output 1* pllde0 = pllde_inref 6 x r/w 0* unde?ned 5 to 4 pllde_nosc[1:0] r/w pll double edge n oscillator 00* div_by_1; pll output frequency range = (80 to 150) msample/s 01 div_by_2; pll output frequency range = (40 to 80) msample/s 10 div_by_4; pll output frequency range = (20 to 40) msample/s 11 div_by_8; pll output frequency range = (10 to 20) msample/s 3 x r/w 0* unde?ned
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 61 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 2 to 1 pllde_iz[1:0] r/w pll double edge zero current 00* iz / 5 01 iz / 10 10 iz / 15 11 iz / 20 0 pllde_fdn r/w pll double edge fdn 0 normal (pll loop active) 1* standby (pll loop open) table 77. ccir_div register (address 0ch) bit description legend: * = default value bit symbol access value description 7 to 1 x r/w 0000 000* unde?ned 0 refdiv2 r/w reference divider 2 0 pllde_inref = pllclkin 1* pllde_inref = pllclkin / 2 table 78. vai_pll register (address 0dh) bit description legend: * = default value bit symbol access value description 7 x r 0* unde?ned 6 pllde_hvp r pll de high voltage protection 0* pllde high voltage protection cell output is 0 1 pllde high voltage protection cell output is 1 5 pllscg_hvp r pll scg high voltage protection 0* pllscg high voltage protection cell output is 0 1 pllscg high voltage protection cell output is 1 4 pllsrl_hvp r pll srl high voltage protection 0* pllsrl high voltage protection cell output is 0 1 pllsrl high voltage protection cell output is 1 3 x r 0* unde?ned 2 pllde_lock r pll de locked 0* pllde not locked 1 pllde in lock 1 pllscg_lock r pll scg locked 0* pllscg not locked 1 pllscg in lock 0 pllsrl_lock r pll srl locked 0* pllsrl not locked 1 pllsrl in lock table 76. pll_de register (address 0bh) bit description continued legend: * = default value bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 62 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 79. audio_div register (address 0eh) bit description legend: * = default value bit symbol access value description 7 to 3 x r/w 0000 0* unde?ned 2 to 0 audio_div[2:0] r/w audio divider: not guaranteed; under reservation (ip_manual) 000 audio_clk_out = serclk / 1 001 audio_clk_out = serclk / 2 010 audio_clk_out = serclk / 4 011* audio_clk_out = serclk / 8 100 audio_clk_out = serclk / 16 101 audio_clk_out = serclk / 32 11x do not use table 80. testx registers (address 0fh and 10h) bit description legend: * = default value address register bit symbol access value description 0fh test1 7 to 5 x r/w 000* unde?ned 4 tstserphoe r/w test serializer phoe 0* srl_tst_ph2_o = '0'; srl_tst_ph3_o = '0' 1 srl_tst_ph2_o = 'active'; srl_tst_ph3_o = 'active' 3 to 2 x r/w 00* unde?ned 1 tst_nosc r/w test n oscillator: test mode nosc predividers 0* normal mode; input nosc predivider = pll oscillator output 1 test mode; input nosc predivider = pll reference input 0 tst_hvp r/w test high voltage protection: test high voltage protection cells 0* normal pll mode 1 test mode; hvp input forced to v dda(pll_3v3) 10h test2 7 to 2 x r/w 0000 00* unde?ned 1 pwd1v8 r/w power-down 1.8 v 0* normal operation 1 sleep mode plls 0 divtestoe r/w divider tests output enable: enable activity of scaler pll dividers test outputs 0* test outputs = '0' 1 test outputs = active
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 63 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.5.2 current page address register 9.6 information frames and packets page register de?nitions the current page address for the information frames and packets page is 10h. the con?guration of the registers for this page is given in t ab le 83 . table 81. sel_clk register (address 11h) bit description legend: * = default value bit symbol access value description 7 to 4 x r/w 0000* unde?ned 3 ena_sc_clk r/w enable scaler clocks 0* disable scaler clocks (sc_clk_m, clk1_m) 1 enable scaler clocks (sc_clk_m, clk1_m) 2 to 1 sel_vrf_clk[1:0] r/w select video reformatter clock 00* vrf_clk_m = not tmdsclkpo; sc_clk_m = tmdsclkpo 01 vrf_clk_m = scaclko_pllscgon; sc_clk_m = not scaclko_pllscgon 10 vrf_clk_m = scaclko_tmdsclkn; sc_clk_m = not scaclko_tmdsclkn 11 vrf_clk_m = scaclko_tmdsclkn; sc_clk_m = not scaclko_tmdsclkn 0 sel_clk1 r/w select clock 1 0* clk1_m = not (plldeo) 1 clk1_m = plldeo_div2 table 82. curpage_adr register (address ffh) bit description legend: * = default value bit symbol access value description 7 to 0 curpage_adr[7:0] w 00h* current page address: selects the current memory page
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 64 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 83. i 2 c-bus registers of memory page 10h [1] register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb) not used 00h - - 0000 0000 ::: : : not used 1fh - - 0000 0000 vsp_if_type 20h r/w vsp_if_type[7:0] 1000 0001 vsp_if_version 21h r/w vsp_if_version[7:0] 0000 0000 vsp_if_length 22h r/w x x x vsp_if_length[4:0] 0000 0000 vsp_if_checksum 23h r/w vsp_if_checksum[7:0] 0000 0000 vsp_if_ieee_lsb 24h r/w vsp_if_ieee[7:0] 0000 0000 vsp_if_ieee_isb 25h r/w vsp_if_ieee[15:8] 0000 0000 vsp_if_ieee_msb 26h r/w vsp_if_ieee[23:16] 0000 0000 vsp_if_byte4 27h r/w vsp_if_pb4[7:0] 0000 0000 vsp_if_byte5 28h r/w vsp_if_pb5[7:0] 0000 0000 vsp_if_byte6 29h r/w vsp_if_pb6[7:0] 0000 0000 vsp_if_byte7 2ah r/w vsp_if_pb7[7:0] 0000 0000 vsp_if_byte8 2bh r/w vsp_if_pb8[7:0] 0000 0000 vsp_if_byte9 2ch r/w vsp_if_pb9[7:0] 0000 0000 vsp_if_byte10 2dh r/w vsp_if_pb10[7:0] 0000 0000 vsp_if_byte11 2eh r/w vsp_if_pb11[7:0] 0000 0000 vsp_if_byte12 2fh r/w vsp_if_pb12[7:0] 0000 0000 vsp_if_byte13 30h r/w vsp_if_pb13[7:0] 0000 0000 vsp_if_byte14 31h r/w vsp_if_pb14[7:0] 0000 0000 vsp_if_byte15 32h r/w vsp_if_pb15[7:0] 0000 0000 vsp_if_byte16 33h r/w vsp_if_pb16[7:0] 0000 0000 vsp_if_byte17 34h r/w vsp_if_pb17[7:0] 0000 0000 vsp_if_byte18 35h r/w vsp_if_pb18[7:0] 0000 0000 vsp_if_byte19 36h r/w vsp_if_pb19[7:0] 0000 0000 vsp_if_byte20 37h r/w vsp_if_pb20[7:0] 0000 0000 vsp_if_byte21 38h r/w vsp_if_pb21[7:0] 0000 0000 vsp_if_byte22 39h r/w vsp_if_pb22[7:0] 0000 0000 vsp_if_byte23 3ah r/w vsp_if_pb23[7:0] 0000 0000 vsp_if_byte24 3bh r/w vsp_if_pb24[7:0] 0000 0000 vsp_if_byte25 3ch r/w vsp_if_pb25[7:0] 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 65 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter vsp_if_byte26 3dh r/w vsp_if_pb26[7:0] 0000 0000 vsp_if_byte27 3eh r/w vsp_if_pb27[7:0] 0000 0000 not used 3fh - - 0000 0000 avi_if_type 40h r/w avi_if_type[7:0] 1000 0010 avi_if_version 41h r/w avi_if_version[7:0] 0000 0000 avi_if_length 42h r/w x x x avi_if_length[4:0] 0000 0000 avi_if_checksum 43h r/w avi_if_checksum[7:0] 0000 0000 avi_if_byte1 44h r/w reserved avi_if_y[1:0] avi_if_a avi_if_b[1:0] avi_if_s[1:0] 0000 0000 avi_if_byte2 45h r/w avi_if_c[1:0] avi_if_m[1:0] avi_if_r[3:0] 0000 0000 avi_if_byte3 46h r/w reserved avi_if_sc[1:0] 0000 0000 avi_if_byte4 47h r/w reserved avi_if_vic[6:0] 0000 0000 avi_if_byte5 48h r/w reserved avi_if_pr[3:0] 0000 0000 avi_if_byte6 49h r/w line_e_tp_bar[7:0] 0000 0000 avi_if_byte7 4ah r/w line_e_tp_bar[15:8] 0000 0000 avi_if_byte8 4bh r/w line_s_bt_bar[7:0] 0000 0000 avi_if_byte9 4ch r/w line_s_bt_bar[15:8] 0000 0000 avi_if_byte10 4dh r/w pix_e_lf_bar[7:0] 0000 0000 avi_if_byte11 4eh r/w pix_e_lf_bar[15:8] 0000 0000 avi_if_byte12 4fh r/w pix_s_rg_bar[7:0] 0000 0000 avi_if_byte13 50h r/w pix_s_rg_bar[15:8] 0000 0000 avi_if_byte14 51h r/w avi_if_rb14[7:0] 0000 0000 avi_if_byte15 52h r/w avi_if_rb15[7:0] 0000 0000 avi_if_byte16 53h r/w avi_if_rb16[7:0] 0000 0000 avi_if_byte17 54h r/w avi_if_rb17[7:0] 0000 0000 avi_if_byte18 55h r/w avi_if_rb18[7:0] 0000 0000 avi_if_byte19 56h r/w avi_if_rb19[7:0] 0000 0000 avi_if_byte20 57h r/w avi_if_rb20[7:0] 0000 0000 avi_if_byte21 58h r/w avi_if_rb21[7:0] 0000 0000 avi_if_byte22 59h r/w avi_if_rb22[7:0] 0000 0000 avi_if_byte23 5ah r/w avi_if_rb23[7:0] 0000 0000 avi_if_byte24 5bh r/w avi_if_rb24[7:0] 0000 0000 avi_if_byte25 5ch r/w avi_if_rb25[7:0] 0000 0000 table 83. i 2 c-bus registers of memory page 10h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 66 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter avi_if_byte26 5dh r/w avi_if_rb26[7:0] 0000 0000 avi_if_byte27 5eh r/w avi_if_rb27[7:0] 0000 0000 not used 5fh - - 0000 0000 spd_if_type 60h r/w spd_if_type[7:0] 1000 0011 spd_if_version 61h r/w spd_if_version[7:0] 0000 0000 spd_if_length 62h r/w x x x spd_if_length[4:0] 0000 0000 spd_if_checksum 63h r/w spd_if_checksum[7:0] 0000 0000 spd_if_byte1 64h r/w x spd_if_vn1[6:0] 0000 0000 spd_if_byte2 65h r/w x spd_if_vn2[6:0] 0000 0000 spd_if_byte3 66h r/w x spd_if_vn3[6:0] 0000 0000 spd_if_byte4 67h r/w x spd_if_vn4[6:0] 0000 0000 spd_if_byte5 68h r/w x spd_if_vn5[6:0] 0000 0000 spd_if_byte6 69h r/w x spd_if_vn6[6:0] 0000 0000 spd_if_byte7 6ah r/w x spd_if_vn7[6:0] 0000 0000 spd_if_byte8 6bh r/w x spd_if_vn8[6:0] 0000 0000 spd_if_byte9 6ch r/w x spd_if_pd1[6:0] 0000 0000 spd_if_byte10 6dh r/w x spd_if_pd2[6:0] 0000 0000 spd_if_byte11 6eh r/w x spd_if_pd3[6:0] 0000 0000 spd_if_byte12 6fh r/w x spd_if_pd4[6:0] 0000 0000 spd_if_byte13 70h r/w x spd_if_pd5[6:0] 0000 0000 spd_if_byte14 71h r/w x spd_if_pd6[6:0] 0000 0000 spd_if_byte15 72h r/w x spd_if_pd7[6:0] 0000 0000 spd_if_byte16 73h r/w x spd_if_pd8[6:0] 0000 0000 spd_if_byte17 74h r/w x spd_if_pd9[6:0] 0000 0000 spd_if_byte18 75h r/w x spd_if_pd10[6:0] 0000 0000 spd_if_byte19 76h r/w x spd_if_pd11[6:0] 0000 0000 spd_if_byte20 77h r/w x spd_if_pd12[6:0] 0000 0000 spd_if_byte21 78h r/w x spd_if_pd13[6:0] 0000 0000 spd_if_byte22 79h r/w x spd_if_pd14[6:0] 0000 0000 spd_if_byte23 7ah r/w x spd_if_pd15[6:0] 0000 0000 spd_if_byte24 7bh r/w x spd_if_pd16[6:0] 0000 0000 spd_if_byte25 7ch r/w spd_if_sdi[7:0] 0000 0000 table 83. i 2 c-bus registers of memory page 10h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 67 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter spd_if_byte26 7dh r/w spd_if_byte26[7:0] 0000 0000 spd_if_byte27 7eh r/w spd_if_byte27[7:0] 0000 0000 not used 7fh - - 0000 0000 aud_if_type 80h r/w aud_if_type[7:0] 1000 0100 aud_if_version 81h r/w aud_if_version[7:0] 0000 0000 aud_if_length 82h r/w x x x aud_if_length[4:0] 0000 0000 aud_if_checksum 83h r/w aud_if_checksum[7:0] 0000 0000 aud_if_byte1 84h r/w aud_if_ct[3:0] reserved aud_if_cc[2:0] 0000 0000 aud_if_byte2 85h r/w reserved aud_if_sf[2:0] aud_if_ss[1:0] 0000 0000 aud_if_byte3 86h r/w aud_if_byte3[7:0] 0000 0000 aud_if_byte4 87h r/w aud_if_ca[7:0] 0000 0000 aud_if_byte5 88h r/w aud_if_ dm_inh aud_if_lsv[3:0] reserved 0000 0000 aud_if_byte6 89h r/w aud_if_byte6[7:0] 0000 0000 aud_if_byte7 8ah r/w aud_if_byte7[7:0] 0000 0000 aud_if_byte8 8bh r/w aud_if_byte8[7:0] 0000 0000 aud_if_byte9 8ch r/w aud_if_byte9[7:0] 0000 0000 aud_if_byte10 8dh r/w aud_if_byte10[7:0] 0000 0000 aud_if_byte11 8eh r/w aud_if_byte11[7:0] 0000 0000 aud_if_byte12 8fh r/w aud_if_byte12[7:0] 0000 0000 aud_if_byte13 90h r/w aud_if_byte13[7:0] 0000 0000 aud_if_byte14 91h r/w aud_if_byte14[7:0] 0000 0000 aud_if_byte15 92h r/w aud_if_byte15[7:0] 0000 0000 aud_if_byte16 93h r/w aud_if_byte16[7:0] 0000 0000 aud_if_byte17 94h r/w aud_if_byte17[7:0] 0000 0000 aud_if_byte18 95h r/w aud_if_byte18[7:0] 0000 0000 aud_if_byte19 96h r/w aud_if_byte19[7:0] 0000 0000 aud_if_byte20 97h r/w aud_if_byte20[7:0] 0000 0000 aud_if_byte21 98h r/w aud_if_byte21[7:0] 0000 0000 aud_if_byte22 99h r/w aud_if_byte22[7:0] 0000 0000 aud_if_byte23 9ah r/w aud_if_byte23[7:0] 0000 0000 aud_if_byte24 9bh r/w aud_if_byte24[7:0] 0000 0000 table 83. i 2 c-bus registers of memory page 10h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 68 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter aud_if_byte25 9ch r/w aud_if_byte25[7:0] 0000 0000 aud_if_byte26 9dh r/w aud_if_byte26[7:0] 0000 0000 aud_if_byte27 9eh r/w aud_if_byte27[7:0] 0000 0000 not used 9fh - - 0000 0000 mps_if_type a0h r/w mps_if_type[7:0] 1000 0101 mps_if_version a1h r/w mps_if_version[7:0] 0000 0000 mps_if_length a2h r/w x x x mps_if_length[4:0] 0000 0000 mps_if_checksum a3h r/w mps_if_checksum[7:0] 0000 0000 mps_if_byte1 a4h r/w mps_if_mb0[7:0] 0000 0000 mps_if_byte2 a5h r/w mps_if_mb1[7:0] 0000 0000 mps_if_byte3 a6h r/w mps_if_mb2[7:0] 0000 0000 mps_if_byte4 a7h r/w mps_if_mb3[7:0] 0000 0000 mps_if_byte5 a8h r/w reserved mps_if_ fr0 reserved mps_if_mf[1:0] 0000 0000 mps_if_byte6 a9h r/w mps_if_byte6[7:0] 0000 0000 mps_if_byte7 aah r/w mps_if_byte7[7:0] 0000 0000 mps_if_byte8 abh r/w mps_if_byte8[7:0] 0000 0000 mps_if_byte9 ach r/w mps_if_byte9[7:0] 0000 0000 mps_if_byte10 adh r/w mps_if_byte10[7:0] 0000 0000 mps_if_byte11 aeh r/w mps_if_byte11[7:0] 0000 0000 mps_if_byte12 afh r/w mps_if_byte12[7:0] 0000 0000 mps_if_byte13 b0h r/w mps_if_byte13[7:0] 0000 0000 mps_if_byte14 b1h r/w mps_if_byte14[7:0] 0000 0000 mps_if_byte15 b2h r/w mps_if_byte15[7:0] 0000 0000 mps_if_byte16 b3h r/w mps_if_byte16[7:0] 0000 0000 mps_if_byte17 b4h r/w mps_if_byte17[7:0] 0000 0000 mps_if_byte18 b5h r/w mps_if_byte18[7:0] 0000 0000 mps_if_byte19 b6h r/w mps_if_byte19[7:0] 0000 0000 mps_if_byte20 b7h r/w mps_if_byte20[7:0] 0000 0000 mps_if_byte21 b8h r/w mps_if_byte21[7:0] 0000 0000 mps_if_byte22 b9h r/w mps_if_byte22[7:0] 0000 0000 mps_if_byte23 bah r/w mps_if_byte23[7:0] 0000 0000 table 83. i 2 c-bus registers of memory page 10h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 69 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] r: reading register w: writing register x: bit must be set to default value for proper operation -: not used mps_if_byte24 bbh r/w mps_if_byte24[7:0] 0000 0000 mps_if_byte25 bch r/w mps_if_byte25[7:0] 0000 0000 mps_if_byte26 bdh r/w mps_if_byte26[7:0] 0000 0000 mps_if_byte27 beh r/w mps_if_byte27[7:0] 0000 0000 not used bfh - - 0000 0000 ::: : : not used feh - - 0000 0000 curpage_adr ffh w curpage_adr[7:0] 0000 0000 table 83. i 2 c-bus registers of memory page 10h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 70 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.6.1 vendor-speci?c infoframe registers below is an example of use. please refer to eia/cea-861b speci?cation and hdmi 1.2a speci?cation for the correct de?nition of data bytes. table 84. vsp_if_xx registers (address 20h to 3eh) bit description legend: * = default value address register bit symbol access value description 20h vsp_if_type 7 to 0 vsp_if_type[7:0] r/w 81h* vendor-speci?c infoframe packet type: gives the packet type of the vendor-speci?c infoframe packet (80h + infoframe type code as per eia/cea-861b ) 21h vsp_if_version 7 to 0 vsp_if_ version[7:0] r/w 00h* vendor-speci?c infoframe version: gives the version number of the vendor-speci?c infoframe 22h vsp_if_length 7 to 5 x r/w 000* reserved (shall be 000) 4 to 0 vsp_if_ length[4:0] r/w 0 0000* vendor-speci?c infoframe length: gives the number of data bytes for the vendor-speci?c infoframe; this length does not include the checksum 23h vsp_if_ checksum 7 to 0 vsp_if_ checksum[7:0] r/w 00h* vendor-speci?c infoframe checksum: shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the vendor-speci?c infoframe packet contents (determined by infoframe length) plus the checksum itself equals 0 24h vsp_if_ieee_lsb 7 to 0 vsp_if_ieee[7:0] r/w 00h* vendor-speci?c infoframe ieee: 24-bit ieee registration identi?er 25h vsp_if_ieee_isb 7 to 0 vsp_if_ieee[15:8] r/w 00h* 26h vsp_if_ieee_msb 7 to 0 vsp_if_ieee[23:16] r/w 00h* vendor-speci?c infoframe payload byte x: x = 4 to 27 27h vsp_if_byte4 7 to 0 vsp_if_pb4[7:0] r/w 00h* byte 4 28h vsp_if_byte5 7 to 0 vsp_if_pb5[7:0] r/w 00h* byte 5 29h vsp_if_byte6 7 to 0 vsp_if_pb6[7:0] r/w 00h* byte 6 2ah vsp_if_byte7 7 to 0 vsp_if_pb7[7:0] r/w 00h* byte 7 2bh vsp_if_byte8 7 to 0 vsp_if_pb8[7:0] r/w 00h* byte 8 2ch vsp_if_byte9 7 to 0 vsp_if_pb9[7:0] r/w 00h* byte 9 2dh vsp_if_byte10 7 to 0 vsp_if_pb10[7:0] r/w 00h* byte 10 2eh vsp_if_byte11 7 to 0 vsp_if_pb11[7:0] r/w 00h* byte 11 2fh vsp_if_byte12 7 to 0 vsp_if_pb12[7:0] r/w 00h* byte 12 30h vsp_if_byte13 7 to 0 vsp_if_pb13[7:0] r/w 00h* byte 13 31h vsp_if_byte14 7 to 0 vsp_if_pb14[7:0] r/w 00h* byte 14 32h vsp_if_byte15 7 to 0 vsp_if_pb15[7:0] r/w 00h* byte 15 33h vsp_if_byte16 7 to 0 vsp_if_pb16[7:0] r/w 00h* byte 16 34h vsp_if_byte17 7 to 0 vsp_if_pb17[7:0] r/w 00h* byte 17 35h vsp_if_byte18 7 to 0 vsp_if_pb18[7:0] r/w 00h* byte 18 36h vsp_if_byte19 7 to 0 vsp_if_pb19[7:0] r/w 00h* byte 19
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 71 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.6.2 auxiliary video information infoframe registers below is an example of use. please refer to eia/cea-861b speci?cation and hdmi 1.2a speci?cation for the correct de?nition of data bytes. 37h vsp_if_byte20 7 to 0 vsp_if_pb20[7:0] r/w 00h* byte 20 38h vsp_if_byte21 7 to 0 vsp_if_pb21[7:0] r/w 00h* byte 21 39h vsp_if_byte22 7 to 0 vsp_if_pb22[7:0] r/w 00h* byte 22 3ah vsp_if_byte23 7 to 0 vsp_if_pb23[7:0] r/w 00h* byte 23 3bh vsp_if_byte24 7 to 0 vsp_if_pb24[7:0] r/w 00h* byte 24 3ch vsp_if_byte25 7 to 0 vsp_if_pb25[7:0] r/w 00h* byte 25 3dh vsp_if_byte26 7 to 0 vsp_if_pb26[7:0] r/w 00h* byte 26 3eh vsp_if_byte27 7 to 0 vsp_if_pb27[7:0] r/w 00h* byte 27 table 84. vsp_if_xx registers (address 20h to 3eh) bit description continued legend: * = default value address register bit symbol access value description table 85. avi_if_xx registers (address 40h to 5eh) bit description legend: * = default value address register bit symbol access value description 40h avi_if_type 7 to 0 avi_if_type[7:0] r/w 82h* auxiliary video information infoframe packet type: gives the packet type of the auxiliary video information infoframe packet (80h + infoframe type code as per eia/cea-861b ) 41h avi_if_version 7 to 0 avi_if_version[7:0] r/w 00h* auxiliary video information infoframe version: gives the version number of the auxiliary video information infoframe 42h avi_if_length 7 to 5 x r/w 000* reserved (shall be 000) 4 to 0 avi_if_length[4:0] r/w 0 0000* auxiliary video information infoframe length: gives the number of data bytes for the auxiliary video information infoframe; this length does not include the checksum 43h avi_if_ checksum 7 to 0 avi_if_ checksum[7:0] r/w 00h* auxiliary video information infoframe checksum: shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the auxiliary video information infoframe packet contents (determined by infoframe length) plus the checksum itself equals 0
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 72 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 44h avi_if_byte1 7 reserved r/w 0* reserved (shall be zero) 6 to 5 avi_if_y[1:0] r/w auxiliary video information infoframe y : rgb or yc b c r indicator 00* rgb 01 yc b c r 4 : 2 : 2 10 yc b c r 4 : 4 : 4 11 future 4 avi_if_a r/w auxiliary video information infoframe a : active format information present 0* no data 1 active format information valid 3 to 2 avi_if_b[1:0] r/w auxiliary video information infoframe bar: bar information 00* bar data not valid 01 vertical bar info valid 10 horizontal bar info valid 11 vertical and horizontal bar info valid 1 to 0 avi_if_s[1:0] r/w auxiliary video information infoframe scan: scan information 00* no data 01 overscanned (television) 10 underscanned (computer) 11 future 45h avi_if_byte2 7 to 6 avi_if_c[1:0] r/w auxiliary video information infoframe colorimetry : colorimetry 00* no data 01 itu601 10 itu709 11 future 5 to 4 avi_if_m[1:0] r/w auxiliary video information infoframe m : picture aspect ratio 00* no data 01 4 : 3 10 16 : 9 11 future 3 to 0 avi_if_r[3:0] r/w auxiliary video information infoframe ratio : active format aspect ratio 1000 same as picture aspect ratio 1001 4 : 3 (center) 1010 16 : 9 (center) 1011 14 : 9 (center) other per dvb afd active_format ?eld table 85. avi_if_xx registers (address 40h to 5eh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 73 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 46h avi_if_byte3 7 to 2 reserved r/w 0000 00* reserved (shall be zero) 1 to 0 avi_if_sc[1:0] r/w auxiliary video information infoframe scaling : non-uniform picture scaling 00* no known non-uniform scaling 01 picture has been scaled horizontally 10 picture has been scaled vertically 11 picture has been scaled horizontally and vertically 47h avi_if_byte4 7 reserved r/w 0* reserved (shall be zero) 6 to 0 avi_if_vic[6:0] r/w 000 0000* auxiliary video information infoframe video identi?cation code : video identi?cation code 48h avi_if_byte5 7 to 4 reserved r/w 0000* reserved (shall be zero) 3 to 0 avi_if_pr[3:0] r/w 0000* auxiliary video information infoframe pixel repetition : pixel repetition 49h avi_if_byte6 7 to 0 line_e_tp_bar[7:0] r/w 00h* line number of end of top bar 4ah avi_if_byte7 7 to 0 line_e_tp_bar[15:8] r/w 00h* 4bh avi_if_byte8 7 to 0 line_s_bt_bar[7:0] r/w 00h* line number of start of bottom bar 4ch avi_if_byte9 7 to 0 line_s_bt_bar[15:8] r/w 00h* 4dh avi_if_byte10 7 to 0 pix_e_lf_bar[7:0] r/w 00h* pixel number of end of left bar 4eh avi_if_byte11 7 to 0 pix_e_lf_bar[15:8] r/w 00h* 4fh avi_if_byte12 7 to 0 pix_s_rg_bar[7:0] r/w 00h* pixel number of start of right bar 50h avi_if_byte13 7 to 0 pix_s_rg_bar[15:8] r/w 00h* auxiliary video information infoframe reserved byte x: x = 14 to 27 51h avi_if_byte14 7 to 0 avi_if_rb14[7:0] r/w 00h* byte 14; reserved (shall be zero) 52h avi_if_byte15 7 to 0 avi_if_rb15[7:0] r/w 00h* byte 15; reserved (shall be zero) 53h avi_if_byte16 7 to 0 avi_if_rb16[7:0] r/w 00h* byte 16; reserved (shall be zero) 54h avi_if_byte17 7 to 0 avi_if_rb17[7:0] r/w 00h* byte 17; reserved (shall be zero) 55h avi_if_byte18 7 to 0 avi_if_rb18[7:0] r/w 00h* byte 18; reserved (shall be zero) 56h avi_if_byte19 7 to 0 avi_if_rb19[7:0] r/w 00h* byte 19; reserved (shall be zero) 57h avi_if_byte20 7 to 0 avi_if_rb20[7:0] r/w 00h* byte 20; reserved (shall be zero) 58h avi_if_byte21 7 to 0 avi_if_rb21[7:0] r/w 00h* byte 21; reserved (shall be zero) 59h avi_if_byte22 7 to 0 avi_if_rb22[7:0] r/w 00h* byte 22; reserved (shall be zero) 5ah avi_if_byte23 7 to 0 avi_if_rb23[7:0] r/w 00h* byte 23; reserved (shall be zero) 5bh avi_if_byte24 7 to 0 avi_if_rb24[7:0] r/w 00h* byte 24; reserved (shall be zero) 5ch avi_if_byte25 7 to 0 avi_if_rb25[7:0] r/w 00h* byte 25; reserved (shall be zero) 5dh avi_if_byte26 7 to 0 avi_if_rb26[7:0] r/w 00h* byte 26; reserved (shall be zero) 5eh avi_if_byte27 7 to 0 avi_if_rb27[7:0] r/w 00h* byte 27; reserved (shall be zero) table 85. avi_if_xx registers (address 40h to 5eh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 74 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.6.3 source product description infoframe registers below is an example of use. please refer to eia/cea-861b speci?cation and hdmi 1.2a speci?cation for the correct de?nition of data bytes. table 86. spd_if_xx registers (address 60h to 7eh) bit description legend: * = default value address register bit symbol access value description 60h spd_if_type 7 to 0 spd_if_type[7:0] r/w 83h* source product description infoframe packet type: gives the packet type of the source product description infoframe packet (80h + infoframe type code as per eia/cea-861b ) 61h spd_if_version 7 to 0 spd_if_ version[7:0] r/w 00h* source product description infoframe version : gives the version number of the source product description infoframe 62h spd_if_length 7 to 5 x r/w 000* reserved (shall be 000) 4 to 0 spd_if_length[4:0] r/w 0 0000* source product description infoframe length : gives the number of data bytes for the source product description infoframe; this length does not include the checksum 63h spd_if_checksum 7 to 0 spd_if_ checksum[7:0] r/w 00h* source product description infoframe checksum : shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the source product description infoframe packet contents (determined by infoframe length) plus the checksum itself equals 0 source product description infoframe vendor name : 7-bit ascii code 64h spd_if_byte1 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_vn1[6:0] r/w 000 0000* character 1 65h spd_if_byte2 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_vn2[6:0] r/w 000 0000* character 2 66h spd_if_byte3 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_vn3[6:0] r/w 000 0000* character 3 67h spd_if_byte4 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_vn4[6:0] r/w 000 0000* character 4 68h spd_if_byte5 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_vn5[6:0] r/w 000 0000* character 5 69h spd_if_byte6 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_vn6[6:0] r/w 000 0000* character 6 6ah spd_if_byte7 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_vn7[6:0] r/w 000 0000* character 7
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 75 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 6bh spd_if_byte8 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_vn8[6:0] r/w 000 0000* character 8 source product description infoframe product description : 7-bit ascii code 6ch spd_if_byte9 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd1[6:0] r/w 000 0000* character 1 6dh spd_if_byte10 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd2[6:0] r/w 000 0000* character 2 6eh spd_if_byte11 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd3[6:0] r/w 000 0000* character 3 6fh spd_if_byte12 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd4[6:0] r/w 000 0000* character 4 70h spd_if_byte13 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd5[6:0] r/w 000 0000* character 5 71h spd_if_byte14 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd6[6:0] r/w 000 0000* character 6 72h spd_if_byte15 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd7[6:0] r/w 000 0000* character 7 73h spd_if_byte16 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd8[6:0] r/w 000 0000* character 8 74h spd_if_byte17 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd9[6:0] r/w 000 0000* character 9 75h spd_if_byte18 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd10[6:0] r/w 000 0000* character 10 76h spd_if_byte19 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd11[6:0] r/w 000 0000* character 11 77h spd_if_byte20 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd12[6:0] r/w 000 0000* character 12 78h spd_if_byte21 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd13[6:0] r/w 000 0000* character 13 79h spd_if_byte22 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd14[6:0] r/w 000 0000* character 14 7ah spd_if_byte23 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd15[6:0] r/w 000 0000* character 15 7bh spd_if_byte24 7 x r/w 0* reserved (shall be zero) 6 to 0 spd_if_pd16[6:0] r/w 000 0000* character 16 table 86. spd_if_xx registers (address 60h to 7eh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 76 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.6.4 audio infoframe registers below is an example of use. please refer to eia/cea-861b speci?cation and hdmi 1.2a speci?cation for the correct de?nition of data bytes. 7ch spd_if_byte25 7 to 0 spd_if_sdi[7:0] r/w source product description infoframe source device information: source device information 00h* unknown 01h digital stb 02h dvd 03h d-vhs 04h hdd video 05h dvc 06h dsc 07h video cd 08h game 09h pc general source product description infoframe data byte 7dh spd_if_byte26 7 to 0 spd_if_byte26[7:0] r/w 00h* data byte 26 7eh spd_if_byte27 7 to 0 spd_if_byte27[7:0] r/w 00h* data byte 27 table 86. spd_if_xx registers (address 60h to 7eh) bit description continued legend: * = default value address register bit symbol access value description table 87. aud_if_xx registers (address 80h to 9eh) bit description legend: * = default value address register bit symbol access value description 80h aud_if_type 7 to 0 aud_if_type[7:0] r/w 84h* audio infoframe packet type: gives the packet type of the audio infoframe packet (80h + infoframe type code as per eia/cea-861b ) 81h aud_if_version 7 to 0 aud_if_ version[7:0] r/w 00h* audio infoframe version : gives the version number of the audio infoframe 82h aud_if_length 7 to 5 x r/w 000* reserved (shall be zero) 4 to 0 aud_if_length[4:0] r/w 0 0000* audio infoframe length : gives the number of data bytes for the audio infoframe; this length does not include the checksum 83h aud_if_checksum 7 to 0 aud_if_ checksum[7:0] r/w 00h* audio infoframe checksum : shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the audio infoframe packet contents (determined by infoframe length) plus the checksum itself equals 0
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 77 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 84h aud_if_byte1 7 to 4 aud_if_ct[3:0] r/w audio infoframe coding type: audio coding type 0000* refer to stream header 0001 iec 60958 pcm 0010 ac-3 0011 mpeg1 0100 mp3 0101 mpeg2 0110 aac 0111 dts 1000 atrac other unde?ned 3 reserved r/w 0* reserved bit 2 to 0 aud_if_cc[2:0] r/w audio infoframe channel count: audio channel count 000* refer to stream header 001 2 channels 010 3 channels 011 4 channels 100 5 channels 101 6 channels 110 7 channels 111 8 channels 85h aud_if_byte2 7 to 5 reserved r/w 000* reserved (shall be zero) 4 to 2 aud_if_sf[2:0] r/w audio infoframe sampling frequency: sampling frequency 000* refer to stream header 001 32 khz 010 44.1 khz (cd) 011 48 khz 100 88.2 khz 101 96 khz 110 176.4 khz 111 192 khz 1 to 0 aud_if_ss[1:0] r/w audio infoframe sample size: sample size 00* refer to stream header 01 16 bits 10 20 bits 11 24 bits table 87. aud_if_xx registers (address 80h to 9eh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 78 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 86h aud_if_byte3 7 to 0 aud_if_byte3[7:0] r/w 00h* audio infoframe data byte 3: value 8 khz = maximum bit rate of audio stream (compressed audio format) 87h aud_if_byte4 7 to 0 aud_if_ca[7:0] r/w 00h* audio infoframe channel allocation: channel allocation (lpcm) 88h aud_if_byte5 7 aud_if_dm_inh r/w audio infoframe down-mix inhibit ?ag: down-mix inhibit ?ag 0* permitted or no information about any assertion of this 1 prohibited 6 to 3 aud_if_lsv[3:0] r/w audio infoframe level shift value: level shift value 0000* 0 db 0001 1 db 0010 2 db 0011 3 db 1000 4 db :: 1111 15 db 2 to 0 reserved r/w 000* reserved (shall be 000h) audio infoframe data byte x: x = 6 to 27 89h aud_if_byte6 7 to 0 aud_if_byte6[7:0] r/w 00h* byte 6: reserved (shall be zero) 8ah aud_if_byte7 6 to 0 aud_if_byte7[7:0] r/w 00h* byte 7: reserved (shall be zero) 8bh aud_if_byte8 6 to 0 aud_if_byte8[7:0] r/w 00h* byte 8: reserved (shall be zero) 8ch aud_if_byte9 6 to 0 aud_if_byte9[7:0] r/w 00h* byte 9: reserved (shall be zero) 8dh aud_if_byte10 7 to 0 aud_if_byte10[7:0] r/w 00h* byte 10: reserved (shall be zero) 8eh aud_if_byte11 7 to 0 aud_if_byte11[7:0] r/w 00h* byte 11: reserved (shall be zero) 8fh aud_if_byte12 7 to 0 aud_if_byte12[7:0] r/w 00h* byte 12: reserved (shall be zero) 90h aud_if_byte13 7 to 0 aud_if_byte13[7:0] r/w 00h* byte 13: reserved (shall be zero) 91h aud_if_byte14 7 to 0 aud_if_byte14[7:0] r/w 00h* byte 14: reserved (shall be zero) 92h aud_if_byte15 7 to 0 aud_if_byte15[7:0] r/w 00h* byte 15: reserved (shall be zero) 93h aud_if_byte16 7 to 0 aud_if_byte16[7:0] r/w 00h* byte 16: reserved (shall be zero) 94h aud_if_byte17 7 to 0 aud_if_byte17[7:0] r/w 00h* byte 17: reserved (shall be zero) 95h aud_if_byte18 7 to 0 aud_if_byte18[7:0] r/w 00h* byte 18: reserved (shall be zero) 96h aud_if_byte19 7 to 0 aud_if_byte19[7:0] r/w 00h* byte 19: reserved (shall be zero) 97h aud_if_byte20 7 to 0 aud_if_byte20[7:0] r/w 00h* byte 20: reserved (shall be zero) 98h aud_if_byte21 7 to 0 aud_if_byte21[7:0] r/w 00h* byte 21: reserved (shall be zero) 99h aud_if_byte22 7 to 0 aud_if_byte22[7:0] r/w 00h* byte 22: reserved (shall be zero) 9ah aud_if_byte23 7 to 0 aud_if_byte23[7:0] r/w 00h* byte 23: reserved (shall be zero) table 87. aud_if_xx registers (address 80h to 9eh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 79 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.6.5 mpeg source infoframe registers below is an example of use. please refer to eia/cea-861b speci?cation and hdmi 1.2a speci?cation for the correct de?nition of data bytes. 9bh aud_if_byte24 7 to 0 aud_if_byte24[7:0] r/w 00h* byte 24: reserved (shall be zero) 9ch aud_if_byte25 7 to 0 aud_if_byte25[7:0] r/w 00h* byte 25: reserved (shall be zero) 9dh aud_if_byte26 7 to 0 aud_if_byte26[7:0] r/w 00h* byte 26: reserved (shall be zero) 9eh aud_if_byte27 7 to 0 aud_if_byte27[7:0] r/w 00h* byte 27: reserved (shall be zero) table 87. aud_if_xx registers (address 80h to 9eh) bit description continued legend: * = default value address register bit symbol access value description table 88. mps_if_xx registers (address a0h to beh) bit description legend: * = default value address register bit symbol access value description a0h mps_if_type 7 to 0 mps_if_type[7:0] r/w 85h* mpeg source infoframe packet type: gives the packet type of the mpeg source infoframe packet (80h + infoframe type code as per eia/cea-861b ) a1h mps_if_version 7 to 0 mps_if_version[7:0] r/w 00h* mpeg source infoframe version : gives the version number of the mpeg source infoframe a2h mps_if_length 7 to 5 x r/w 000* reserved (shall be zero) 4 to 0 mps_if_length[4:0] r/w 0 0000* mpeg source infoframe length : gives the number of data bytes for the mpeg source infoframe; this length does not include the checksum a3h mps_if_ checksum 7 to 0 mps_if_ checksum[7:0] r/w 00h* mpeg source infoframe checksum : shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the mpeg source infoframe packet contents (determined by infoframe length) plus the checksum itself equals 0 mpeg source infoframe mpeg bit rate (hz) a4h mps_if_byte1 7 to 0 mps_if_mb0[7:0] r/w 00h* mb#0 (lower byte) a5h mps_if_byte2 7 to 0 mps_if_mb1[7:0] r/w 00h* mb#1 (medium byte) a6h mps_if_byte3 7 to 0 mps_if_mb2[7:0] r/w 00h* mb#2 (medium byte) a7h mps_if_byte4 7 to 0 mps_if_mb3[7:0] r/w 00h* mb#3 (upper byte)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 80 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter a8h mps_if_byte5 7 to 5 reserved r/w 000* reserved 4 mps_if_fr0 r/w mpeg source infoframe ?eld repeat 0 : for 3 : 2 pull-down 0* new ?eld (picture) 1 repeated ?eld 3 to 2 reserved r/w 00* reserved 1 to 0 mps_if_mf[1:0] r/w mpeg source infoframe mpeg frame : mpeg frame 00* unknown (no data) 01 i picture 10 b picture 11 p picture mpeg source infoframe byte x: x = 6 to 27 a9h mps_if_byte6 7 to 0 mps_if_byte6[7:0] r/w 00h* byte 6: reserved (shall be zero) aah mps_if_byte7 6 to 0 mps_if_byte7[7:0] r/w 000 0000* byte 7: reserved (shall be zero) abh mps_if_byte8 6 to 0 mps_if_byte8[7:0] r/w 000 0000* byte 8: reserved (shall be zero) ach mps_if_byte9 6 to 0 mps_if_byte9[7:0] r/w 000 0000* byte 9: reserved (shall be zero) adh mps_if_byte10 7 to 0 mps_if_byte10[7:0] r/w 00h* byte 10: reserved (shall be zero) aeh mps_if_byte11 7 to 0 mps_if_byte11[7:0] r/w 00h* byte 11: reserved afh mps_if_byte12 7 to 0 mps_if_byte12[7:0] r/w 00h* byte 12: reserved b0h mps_if_byte13 7 to 0 mps_if_byte13[7:0] r/w 00h* byte 13: reserved b1h mps_if_byte14 7 to 0 mps_if_byte14[7:0] r/w 00h* byte 14: reserved b2h mps_if_byte15 7 to 0 mps_if_byte15[7:0] r/w 00h* byte 15: reserved b3h mps_if_byte16 7 to 0 mps_if_byte16[7:0] r/w 00h* byte 16: reserved b4h mps_if_byte17 7 to 0 mps_if_byte17[7:0] r/w 00h* byte 17: reserved b5h mps_if_byte18 7 to 0 mps_if_byte18[7:0] r/w 00h* byte 18: reserved b6h mps_if_byte19 7 to 0 mps_if_byte19[7:0] r/w 00h* byte 19: reserved b7h mps_if_byte20 7 to 0 mps_if_byte20[7:0] r/w 00h* byte 20: reserved b8h mps_if_byte21 7 to 0 mps_if_byte21[7:0] r/w 00h* byte 21: reserved b9h mps_if_byte22 7 to 0 mps_if_byte22[7:0] r/w 00h* byte 22: reserved bah mps_if_byte23 7 to 0 mps_if_byte23[7:0] r/w 00h* byte 23: reserved bbh mps_if_byte24 7 to 0 mps_if_byte24[7:0] r/w 00h* byte 24: reserved bch mps_if_byte25 7 to 0 mps_if_byte25[7:0] r/w 00h* byte 25: reserved bdh mps_if_byte26 7 to 0 mps_if_byte26[7:0] r/w 00h* byte 26: reserved beh mps_if_byte27 7 to 0 mps_if_byte27[7:0] r/w 00h* byte 27: reserved table 88. mps_if_xx registers (address a0h to beh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 81 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.6.6 current page address register 9.7 audio settings and content info packets page register de?nitions the current page address for the audio settings and content info packets page is 11h. the con?guration of the registers for this page is given in t ab le 90 . table 89. curpage_adr register (address ffh) bit description legend: * = default value bit symbol access value description 7 to 0 curpage_adr[7:0] w 00h* current page address: selects the current memory page
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 82 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 90. i 2 c-bus registers of memory page 11h [1] register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb) aip_cntrl_0 00h r/w x rst_cts acr_man x x layout swap rst_fifo 0000 0000 ca_i2s 01h r/w x x x ca_i2s[4:0] 0000 0000 for test 02h r/w xxxxxxx x 0000 0000 for test 03h r/w xxxxxxx x 0000 0000 latency_rd 04h r/w latency_rd[7:0] 0000 0100 acr_cts_0 05h r/w cts[7:0] 0111 1000 acr_cts_1 06h r/w cts[15:8] 0110 1001 acr_cts_2 07h r/w xxxx cts[19:16] 0000 0000 acr_n_0 08h r/w n[7:0] 0000 0000 acr_n_1 09h r/w n[15:8] 0110 0000 acr_n_2 0ah r/w xxxx n[19:16] 0000 0000 gc_avmute 0bh r/w xxxxxx set_ mute clr_mute 0000 0000 cts_n 0ch r/w x x m_sel[1:0] x k_sel[2:0] 0000 0000 enc_cntrl 0dh r/w xxxx ctl_code[1:0] dc_ctl[1:0] 0000 0100 dip_flags 0eh r/w force_ null null - acp isrc2 isrc1 gc acr 0000 0000 dip_if_flags 0fh r/w x x if5 if4 if3 if2 if1 x 0000 0000 not used 10h - - 0000 0000 ::: : : not used 13h - - 0000 0000 ch_stat_b_0 14h r/w ch_stat_byte_0[7:0] 0000 0000 ch_stat_b_1 15h r/w ch_stat_byte_1[7:0] 0000 0000 ch_stat_b_3 16h r/w ch_stat_byte_3[7:0] 0000 0000 ch_stat_b_4 17h r/w ch_stat_byte_4[7:0] 0000 0000 ch_stat_b_2_ap0_l 18h r/w ch_stat_byte_2_ap0_l[7:0] 0000 0000 ch_stat_b_2_ap0_r 19h r/w ch_stat_byte_2_ap0_r[7:0] 0000 0000 ch_stat_b_2_ap1_l 1ah r/w ch_stat_byte_2_ap1_l[7:0] 0000 0000 ch_stat_b_2_ap1_r 1bh r/w ch_stat_byte_2_ap1_r[7:0] 0000 0000 ch_stat_b_2_ap2_l 1ch r/w ch_stat_byte_2_ap2_l[7:0] 0000 0000 ch_stat_b_2_ap2_r 1dh r/w ch_stat_byte_2_ap2_r[7:0] 0000 0000 ch_stat_b_2_ap3_l 1eh r/w ch_stat_byte_2_ap3_l[7:0] 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 83 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter ch_stat_b_2_ap3_r 1fh r/w ch_stat_byte_2_ap3_r[7:0] 0000 0000 isrc1_packet_type 20h r/w isrc1_packet_type[7:0] 0000 0101 isrc1_ctrl 21h r/w isrc_ cont isrc_ valid isrc1_rsvd[5:3] isrc_status[2:0] 0000 0000 isrc1_rsvd 22h r/w isrc1_rsvd[7:0] 0000 0000 upc_ean_isrc_0 23h r/w upc_ean_isrc_0[7:0] 0000 0000 upc_ean_isrc_1 24h r/w upc_ean_isrc_1[7:0] 0000 0000 upc_ean_isrc_2 25h r/w upc_ean_isrc_2[7:0] 0000 0000 upc_ean_isrc_3 26h r/w upc_ean_isrc_3[7:0] 0000 0000 upc_ean_isrc_4 27h r/w upc_ean_isrc_4[7:0] 0000 0000 upc_ean_isrc_5 28h r/w upc_ean_isrc_5[7:0] 0000 0000 upc_ean_isrc_6 29h r/w upc_ean_isrc_6[7:0] 0000 0000 upc_ean_isrc_7 2ah r/w upc_ean_isrc_7[7:0] 0000 0000 upc_ean_isrc_8 2bh r/w upc_ean_isrc_8[7:0] 0000 0000 upc_ean_isrc_9 2ch r/w upc_ean_isrc_9[7:0] 0000 0000 upc_ean_isrc_10 2dh r/w upc_ean_isrc_10[7:0] 0000 0000 upc_ean_isrc_11 2eh r/w upc_ean_isrc_11[7:0] 0000 0000 upc_ean_isrc_12 2fh r/w upc_ean_isrc_12[7:0] 0000 0000 upc_ean_isrc_13 30h r/w upc_ean_isrc_13[7:0] 0000 0000 upc_ean_isrc_14 31h r/w upc_ean_isrc_14[7:0] 0000 0000 upc_ean_isrc_15 32h r/w upc_ean_isrc_15[7:0] 0000 0000 isrc1_pb16 33h r/w isrc1_pb_byte_16[7:0] 0000 0000 isrc1_pb17 34h r/w isrc1_pb_byte_17[7:0] 0000 0000 isrc1_pb18 35h r/w isrc1_pb_byte_18[7:0] 0000 0000 isrc1_pb19 36h r/w isrc1_pb_byte_19[7:0] 0000 0000 isrc1_pb20 37h r/w isrc1_pb_byte_20[7:0] 0000 0000 isrc1_pb21 38h r/w isrc1_pb_byte_21[7:0] 0000 0000 isrc1_pb22 39h r/w isrc1_pb_byte_22[7:0] 0000 0000 isrc1_pb23 3ah r/w isrc1_pb_byte_23[7:0] 0000 0000 isrc1_pb24 3bh r/w isrc1_pb_byte_24[7:0] 0000 0000 isrc1_pb25 3ch r/w isrc1_pb_byte_25[7:0] 0000 0000 isrc1_pb26 3dh r/w isrc1_pb_byte_26[7:0] 0000 0000 table 90. i 2 c-bus registers of memory page 11h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 84 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter isrc1_pb27 3eh r/w isrc1_pb_byte_27[7:0] 0000 0000 not used 3fh - - 0000 0000 isrc2_packet_type 40h r/w isrc2_packet_type[7:0] 0000 0110 isrc2_rsvd1 41h r/w isrc2_rsvd1[7:0] 0000 0000 isrc2_rsvd2 42h r/w isrc2_rsvd2[7:0] 0000 0000 upc_ean_isrc_16 43h r/w upc_ean_isrc_16[7:0] 0000 0000 upc_ean_isrc_17 44h r/w upc_ean_isrc_17[7:0] 0000 0000 upc_ean_isrc_18 45h r/w upc_ean_isrc_18[7:0] 0000 0000 upc_ean_isrc_19 46h r/w upc_ean_isrc_19[7:0] 0000 0000 upc_ean_isrc_20 47h r/w upc_ean_isrc_20[7:0] 0000 0000 upc_ean_isrc_21 48h r/w upc_ean_isrc_21[7:0] 0000 0000 upc_ean_isrc_22 49h r/w upc_ean_isrc_22[7:0] 0000 0000 upc_ean_isrc_23 4ah r/w upc_ean_isrc_23[7:0] 0000 0000 upc_ean_isrc_24 4bh r/w upc_ean_isrc_24[7:0] 0000 0000 upc_ean_isrc_25 4ch r/w upc_ean_isrc_25[7:0] 0000 0000 upc_ean_isrc_26 4dh r/w upc_ean_isrc_26[7:0] 0000 0000 upc_ean_isrc_27 4eh r/w upc_ean_isrc_27[7:0] 0000 0000 upc_ean_isrc_28 4fh r/w upc_ean_isrc_28[7:0] 0000 0000 upc_ean_isrc_29 50h r/w upc_ean_isrc_29[7:0] 0000 0000 upc_ean_isrc_30 51h r/w upc_ean_isrc_30[7:0] 0000 0000 upc_ean_isrc_31 52h r/w upc_ean_isrc_31[7:0] 0000 0000 isrc2_pb16 53h r/w isrc2_pb_byte_16[7:0] 0000 0000 isrc2_pb17 54h r/w isrc2_pb_byte_17[7:0] 0000 0000 isrc2_pb18 55h r/w isrc2_pb_byte_18[7:0] 0000 0000 isrc2_pb19 56h r/w isrc2_pb_byte_19[7:0] 0000 0000 isrc2_pb20 57h r/w isrc2_pb_byte_20[7:0] 0000 0000 isrc2_pb21 58h r/w isrc2_pb_byte_21[7:0] 0000 0000 isrc2_pb22 59h r/w isrc2_pb_byte_22[7:0] 0000 0000 isrc2_pb23 5ah r/w isrc2_pb_byte_23[7:0] 0000 0000 isrc2_pb24 5bh r/w isrc2_pb_byte_24[7:0] 0000 0000 isrc2_pb25 5ch r/w isrc2_pb_byte_25[7:0] 0000 0000 isrc2_pb26 5dh r/w isrc2_pb_byte_26[7:0] 0000 0000 table 90. i 2 c-bus registers of memory page 11h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 85 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter isrc2_pb27 5eh r/w isrc2_pb_byte_27[7:0] 0000 0000 not used 5fh - - 0000 0000 acp_packet_type 60h r/w acp_packet_type[7:0] 0000 0100 acp_type 61h r/w acp_type[7:0] 0000 0000 acp_rsvd 62h r/w acp_rsvd[7:0] 0000 0000 acp_pb0 63h r/w acp_pb_byte_0[7:0] 0000 0000 acp_pb1 64h r/w acp_pb_byte_1[7:0] 0000 0000 acp_pb2 65h r/w acp_pb_byte_2[7:0] 0000 0000 acp_pb3 66h r/w acp_pb_byte_3[7:0] 0000 0000 acp_pb4 67h r/w acp_pb_byte_4[7:0] 0000 0000 acp_pb5 68h r/w acp_pb_byte_5[7:0] 0000 0000 acp_pb6 69h r/w acp_pb_byte_6[7:0] 0000 0000 acp_pb7 6ah r/w acp_pb_byte_7[7:0] 0000 0000 acp_pb8 6bh r/w acp_pb_byte_8[7:0] 0000 0000 acp_pb9 6ch r/w acp_pb_byte_9[7:0] 0000 0000 acp_pb10 6dh r/w acp_pb_byte_10[7:0] 0000 0000 acp_pb11 6eh r/w acp_pb_byte_11[7:0] 0000 0000 acp_pb12 6fh r/w acp_pb_byte_12[7:0] 0000 0000 acp_pb13 70h r/w acp_pb_byte_13[7:0] 0000 0000 acp_pb14 71h r/w acp_pb_byte_14[7:0] 0000 0000 acp_pb15 72h r/w acp_pb_byte_15[7:0] 0000 0000 acp_pb16 73h r/w acp_pb_byte_16[7:0] 0000 0000 acp_pb17 74h r/w acp_pb_byte_17[7:0] 0000 0000 acp_pb18 75h r/w acp_pb_byte_18[7:0] 0000 0000 acp_pb19 76h r/w acp_pb_byte_19[7:0] 0000 0000 acp_pb20 77h r/w acp_pb_byte_20[7:0] 0000 0000 acp_pb21 78h r/w acp_pb_byte_21[7:0] 0000 0000 acp_pb22 79h r/w acp_pb_byte_22[7:0] 0000 0000 acp_pb23 7ah r/w acp_pb_byte_23[7:0] 0000 0000 acp_pb24 7bh r/w acp_pb_byte_24[7:0] 0000 0000 acp_pb25 7ch r/w acp_pb_byte_25[7:0] 0000 0000 acp_pb26 7dh r/w acp_pb_byte_26[7:0] 0000 0000 table 90. i 2 c-bus registers of memory page 11h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 86 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] r: reading register w: writing register x: bit must be set to default value for proper operation -: not used acp_pb27 7eh r/w acp_pb_byte_27[7:0] 0000 0000 not used 7fh - - 0000 0000 ::: : : not used feh - - 0000 0000 curpage_adr ffh w curpage_adr[7:0] 0000 0000 table 90. i 2 c-bus registers of memory page 11h [1] continued register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 87 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.7.1 audio input processor control registers table 91. aip_cntrl_0 register (address 00h) bit description legend: * = default value bit symbol access value description 7 x r/w 0* unde?ned 6 rst_cts r/w reset cts 0* no speci?c action 1 reset cts generation (soft reset) 5 acr_man r/w audio clock regeneration manual 0* automatic audio clock regeneration time stamp generation 1 manual audio clock regeneration time stamp generation 4 to 3 x r/w 00* unde?ned 2 layout r/w layout 0* set layout 0 1 set layout 1 1 swap r/w 0* swap: for internal use 0 rst_fifo r/w reset fifo 0* no speci?c action 1 reset audio fifo table 92. ca_i2s register (address 01h) bit description legend: * = default value bit symbol access value description 7 to 5 x r/w 000* unde?ned 4 to 0 ca_i2s[4:0] r/w 0 0000* channel allocation i 2 s-bus port: layout 1 table 93. latency_rd register (address 04h) bit description legend: * = default value bit symbol access value description 7 to 0 latency_rd[7:0] r/w 04h* latency read: latency value in audio fifo table 94. acr_cts_x registers (address 05h to 07h) bit description legend: * = default value address register bit symbol access value description 07h acr_cts_2 7 to 4 x r/w 0000* unde?ned 3 to 0 cts[19:16] r/w 0000* cts: audio clock recovery cts value for manual cts settings 06h acr_cts_1 7 to 0 cts[15:8] r/w 69h* 05h acr_cts_0 7 to 0 cts[7:0] r/w 78h*
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 88 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 95. acr_n_x registers (address 08h to 0ah) bit description legend: * = default value address register bit symbol access value description 0ah acr_n_2 7 to 4 x r/w 0000* unde?ned 3 to 0 n[19:16] r/w 0000* n: audio clock recovery n value for manual n-settings 09h acr_n_1 7 to 0 n[15:8] r/w 60h* 08h acr_n_0 7 to 0 n[7:0] r/w 00h* table 96. gc_avmute register (address 0bh) bit description legend: * = default value bit symbol access value description 7 to 2 x r/w 0000 00* unde?ned 1 set_mute r/w set mute: gcp.sb0 (bit 0) 0* no speci?c action 1 set avmute ?ag 0 clr_mute r/w clear mute: gcp.sb0 (bit 4) 0* no speci?c action 1 clear avmute ?ag table 97. cts_n register (address 0ch) bit description legend: * = default value bit symbol access value description 7 to 6 x r/w 00* unde?ned 5 to 4 m_sel[1:0] r/w m select: postdivider mts (measured time stamp) 00* cts = mts 01 cts = mts / 2 10 cts = mts / 4 11 cts = mts / 8 3 x r/w 0* unde?ned 2 to 0 k_sel[2:0] r/w k select: predivider (scales n) 000* k = 1 001 k = 2 010 k = 3 011 k = 4 1xx k = 8 table 98. enc_cntrl register (address 0dh) bit description legend: * = default value bit symbol access value description 7 to 4 x r/w 0000* unde?ned
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 89 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 3 to 2 ctl_code[1:0] r/w control code: force ctl[1:0] 00 ctl[1:0] = 00 (dvi mode) 01* ctl[1:0] = 01 (advised to use in case of hdmi mode) 10 ctl[1:0] = 10 (only for debugging purposes) 11 ctl[1:0] = 11 (only for debugging purposes) 1 to 0 dc_ctl[1:0] r/w disparity counter control 00* video guard band initializes disparity_cnt 01 video_data_enable enables disparity_cnt 10 free-running disparity_cnt 11 unde?ned table 99. dip_flags register (address 0eh) bit description legend: * = default value bit symbol access value description 7 force_null r/w force null 0* no speci?c action 1 insert null-packets continuously 6 null r/w null 0* no speci?c action 1 insert one null-packet (this bit is reset by internal control) 5 - r/w -: data packet header/contents as speci?ed by registers 80h to 9eh 0* no speci?c action 1 insert infoframe in ?rst free slot after the keepout window 4 acp r/w audio content protection: data packet header/contents as speci?ed by registers 60h to 7eh (see t ab le 105 ) 0* no speci?c action 1 insert acp in ?rst free slot after the keepout window 3 isrc2 r/w international standard recording code 2: data packet header/contents as speci?ed by registers 40h to 5eh (see t ab le 104 ) 0* no speci?c action 1 insert isrc2 in ?rst free slot after the keepout window table 98. enc_cntrl register (address 0dh) bit description continued legend: * = default value bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 90 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 2 isrc1 r/w international standard recording code 1: data packet header/contents as speci?ed by registers 20h to 3eh (see t ab le 103 ) 0* no speci?c action 1 insert isrc1 in ?rst free slot after the keepout window 1 gc r/w general control 0* no speci?c action 1 insert general control packet (just after v-pulse) 0 acr r/w audio clock regeneration 0* no speci?c action 1 insert audio clock regeneration packets table 100. dip_if_flags register (address 0fh) bit description legend: * = default value bit symbol access value description 7 to 6 x r/w 00* unde?ned 5 if5 r/w if5: data packet header/contents as speci?ed by registers a0h to beh (page 10h) 0* no speci?c action 1 insert if5 in ?rst free slot after the keepout window 4 if4 r/w if4: data packet header/contents as speci?ed by registers 80h to 9eh (page 10h) 0* no speci?c action 1 insert if4 in ?rst free slot after the keepout window 3 if3 r/w if3: data packet header/contents as speci?ed by registers 60h to 7eh (page 10h) 0* no speci?c action 1 insert if3 in ?rst free slot after the keepout window 2 if2 r/w if2: data packet header/contents as speci?ed by registers 40h to 5eh (page 10h) 0* no speci?c action 1 insert if2 in ?rst free slot after the keepout window 1 if1 r/w if1: data packet header/contents as speci?ed by registers 20h to 3eh (page 10h) 0* no speci?c action 1 insert if1 in ?rst free slot after the keepout window 0 x r/w 0* unde?ned table 99. dip_flags register (address 0eh) bit description continued legend: * = default value bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 91 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.7.2 isrc packets registers below is an example of use. please refer to hdmi 1.2a speci?cation for the correct de?nition of data bytes. see hdmi 1.2a speci?cation, section 8.8 for rules regarding the use of the isrc packets. table 101. ch_stat_b_x channel status bytes 0, 1, 3 and 4 registers (address 14h to 17h) bit description legend: * = default value address register bit symbol access value description channel status byte x: x = 0 to 4 14h ch_stat_b_0 7 to 0 ch_stat_byte_0[7:0] r/w 00h* byte 0 15h ch_stat_b_1 7 to 0 ch_stat_byte_1[7:0] r/w 00h* byte 1 16h ch_stat_b_3 7 to 0 ch_stat_byte_3[7:0] r/w 00h* byte 3 17h ch_stat_b_4 7 to 0 ch_stat_byte_4[7:0] r/w 00h* byte 4 table 102. ch_stat_b_2_apx_n channel status byte 2 registers (address 18h to 1fh) bit description legend: * = default value address register bit symbol access value description channel status byte 2 of audio port x: x = 0 to 3 18h ch_stat_b_2_ap0_l 7 to 0 ch_stat_byte_2_ap0_l[7:0] r/w 00h* audio port 0 left 19h ch_stat_b_2_ap0_r 7 to 0 ch_stat_byte_2_ap0_r[7:0] r/w 00h* audio port 0 right 1ah ch_stat_b_2_ap1_l 7 to 0 ch_stat_byte_2_ap1_l[7:0] r/w 00h* audio port 1 left 1bh ch_stat_b_2_ap1_r 7 to 0 ch_stat_byte_2_ap1_r[7:0] r/w 00h* audio port 1 right 1ch ch_stat_b_2_ap2_l 7 to 0 ch_stat_byte_2_ap2_l[7:0] r/w 00h* audio port 2 left 1dh ch_stat_b_2_ap2_r 7 to 0 ch_stat_byte_2_ap2_r[7:0] r/w 00h* audio port 2 right 1eh ch_stat_b_2_ap3_l 7 to 0 ch_stat_byte_2_ap3_l[7:0] r/w 00h* audio port 3 left 1fh ch_stat_b_2_ap3_r 7 to 0 ch_stat_byte_2_ap3_r[7:0] r/w 00h* audio port 3 right table 103. isrc1 packet registers (address 20h to 3eh) bit description legend: * = default value address register bit symbol access value description 20h isrc1_packet_ type 7 to 0 isrc1_packet_type[7:0] r/w 05h* isrc1 packet type: packet type of the isrc1 packet 21h isrc1_ctrl 7 isrc_cont r/w 0* isrc continued : isrc continued in next packet 6 isrc_valid r/w 0* isrc valid : isrc status and data are valid 5 to 3 isrc1_rsvd[5:3] r/w 000* isrc1 reserved: reserved (shall be zero) 2 to 0 isrc_status[2:0] r/w 000* isrc status 001 starting position 010 intermediate position 100 ending position
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 92 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 22h isrc1_rsvd 7 to 0 isrc1_rsvd[7:0] r/w 00h* isrc1 reserved: reserved (shall be zero) isrc1 data byte x: x = 0 to 15 23h upc_ean_isrc_0 7 to 0 upc_ean_isrc_0[7:0] r/w 00h* upc/ean or isrc byte 0 24h upc_ean_isrc_1 7 to 0 upc_ean_isrc_1[7:0] r/w 00h* upc/ean or isrc byte 1 25h upc_ean_isrc_2 7 to 0 upc_ean_isrc_2[7:0] r/w 00h* upc/ean or isrc byte 2 26h upc_ean_isrc_3 7 to 0 upc_ean_isrc_3[7:0] r/w 00h* upc/ean or isrc byte 3 27h upc_ean_isrc_4 7 to 0 upc_ean_isrc_4[7:0] r/w 00h* upc/ean or isrc byte 4 28h upc_ean_isrc_5 7 to 0 upc_ean_isrc_5[7:0] r/w 00h* upc/ean or isrc byte 5 29h upc_ean_isrc_6 7 to 0 upc_ean_isrc_6[7:0] r/w 00h* upc/ean or isrc byte 6 2ah upc_ean_isrc_7 7 to 0 upc_ean_isrc_7[7:0] r/w 00h* upc/ean or isrc byte 7 2bh upc_ean_isrc_8 7 to 0 upc_ean_isrc_8[7:0] r/w 00h* upc/ean or isrc byte 8 2ch upc_ean_isrc_9 7 to 0 upc_ean_isrc_9[7:0] r/w 00h* upc/ean or isrc byte 9 2dh upc_ean_isrc_10 7 to 0 upc_ean_isrc_10[7:0] r/w 00h* upc/ean or isrc byte 10 2eh upc_ean_isrc_11 7 to 0 upc_ean_isrc_11[7:0] r/w 00h* upc/ean or isrc byte 11 2fh upc_ean_isrc_12 7 to 0 upc_ean_isrc_12[7:0] r/w 00h* upc/ean or isrc byte 12 30h upc_ean_isrc_13 7 to 0 upc_ean_isrc_13[7:0] r/w 00h* upc/ean or isrc byte 13 31h upc_ean_isrc_14 7 to 0 upc_ean_isrc_14[7:0] r/w 00h* upc/ean or isrc byte 14 32h upc_ean_isrc_15 7 to 0 upc_ean_isrc_15[7:0] r/w 00h* upc/ean or isrc byte 15 isrc1 data byte x: x = 16 to 27 33h isrc1_pb16 7 to 0 isrc1_pb_byte_16[7:0] r/w 00h* reserved byte 16 (shall be set to a value of 0) 34h isrc1_pb17 7 to 0 isrc1_pb_byte_17[7:0] r/w 00h* reserved byte 17 (shall be set to a value of 0) 35h isrc1_pb18 7 to 0 isrc1_pb_byte_18[7:0] r/w 00h* reserved byte 18 (shall be set to a value of 0) 36h isrc1_pb19 7 to 0 isrc1_pb_byte_19[7:0] r/w 00h* reserved byte 19 (shall be set to a value of 0) 37h isrc1_pb20 7 to 0 isrc1_pb_byte_20[7:0] r/w 00h* reserved byte 20 (shall be set to a value of 0) 38h isrc1_pb21 7 to 0 isrc1_pb_byte_21[7:0] r/w 00h* reserved byte 21 (shall be set to a value of 0) 39h isrc1_pb22 7 to 0 isrc1_pb_byte_22[7:0] r/w 00h* reserved byte 22 (shall be set to a value of 0) 3ah isrc1_pb23 7 to 0 isrc1_pb_byte_23[7:0] r/w 00h* reserved byte 23 (shall be set to a value of 0) 3bh isrc1_pb24 7 to 0 isrc1_pb_byte_24[7:0] r/w 00h* reserved byte 24 (shall be set to a value of 0) 3ch isrc1_pb25 7 to 0 isrc1_pb_byte_25[7:0] r/w 00h* reserved byte 25 (shall be set to a value of 0) 3dh isrc1_pb26 7 to 0 isrc1_pb_byte_26[7:0] r/w 00h* reserved byte 26 (shall be set to a value of 0) 3eh isrc1_pb27 7 to 0 isrc1_pb_byte_27[7:0] r/w 00h* reserved byte 27 (shall be set to a value of 0) table 103. isrc1 packet registers (address 20h to 3eh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 93 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter table 104. isrc2 packet registers (address 40h to 5eh) bit description legend: * = default value address register bit symbol access value description 40h isrc2_packet_ type 7 to 0 isrc2_packet_type[7:0] r/w 06h* isrc2 packet type: packet type of the isrc2 packet 41h isrc2_rsvd1 7 to 0 isrc2_rsvd1[7:0] r/w 00h* isrc2 reserved 1: reserved (shall be zero) 42h isrc2_rsvd2 7 to 0 isrc2_rsvd2[7:0] r/w 00h* isrc2 reserved 2: reserved (shall be zero) isrc2 data byte x: x = 0 to 15 43h upc_ean_isrc_16 7 to 0 upc_ean_isrc_16[7:0] r/w 00h* upc/ean or isrc byte 16 44h upc_ean_isrc_17 7 to 0 upc_ean_isrc_17[7:0] r/w 00h* upc/ean or isrc byte 17 45h upc_ean_isrc_18 7 to 0 upc_ean_isrc_18[7:0] r/w 00h* upc/ean or isrc byte 18 46h upc_ean_isrc_19 7 to 0 upc_ean_isrc_19[7:0] r/w 00h* upc/ean or isrc byte 19 47h upc_ean_isrc_20 7 to 0 upc_ean_isrc_20[7:0] r/w 00h* upc/ean or isrc byte 20 48h upc_ean_isrc_21 7 to 0 upc_ean_isrc_21[7:0] r/w 00h* upc/ean or isrc byte 21 49h upc_ean_isrc_22 7 to 0 upc_ean_isrc_22[7:0] r/w 00h* upc/ean or isrc byte 22 4ah upc_ean_isrc_23 7 to 0 upc_ean_isrc_23[7:0] r/w 00h* upc/ean or isrc byte 23 4bh upc_ean_isrc_24 7 to 0 upc_ean_isrc_24[7:0] r/w 00h* upc/ean or isrc byte 24 4ch upc_ean_isrc_25 7 to 0 upc_ean_isrc_25[7:0] r/w 00h* upc/ean or isrc byte 25 4dh upc_ean_isrc_26 7 to 0 upc_ean_isrc_26[7:0] r/w 00h* upc/ean or isrc byte 26 4eh upc_ean_isrc_27 7 to 0 upc_ean_isrc_27[7:0] r/w 00h* upc/ean or isrc byte 27 4fh upc_ean_isrc_28 7 to 0 upc_ean_isrc_28[7:0] r/w 00h* upc/ean or isrc byte 28 50h upc_ean_isrc_29 7 to 0 upc_ean_isrc_29[7:0] r/w 00h* upc/ean or isrc byte 29 51h upc_ean_isrc_30 7 to 0 upc_ean_isrc_30[7:0] r/w 00h* upc/ean or isrc byte 30 52h upc_ean_isrc_31 7 to 0 upc_ean_isrc_31[7:0] r/w 00h* upc/ean or isrc byte 31 isrc2 data byte x: x = 16 to 27 53h isrc2_pb16 7 to 0 isrc2_pb_byte_16[7:0] r/w 00h* reserved byte 16 (shall be set to a value of 0) 54h isrc2_pb17 7 to 0 isrc2_pb_byte_17[7:0] r/w 00h* reserved byte 17 (shall be set to a value of 0) 55h isrc2_pb18 7 to 0 isrc2_pb_byte_18[7:0] r/w 00h* reserved byte 18 (shall be set to a value of 0) 56h isrc2_pb19 7 to 0 isrc2_pb_byte_19[7:0] r/w 00h* reserved byte 19 (shall be set to a value of 0) 57h isrc2_pb20 7 to 0 isrc2_pb_byte_20[7:0] r/w 00h* reserved byte 20 (shall be set to a value of 0) 58h isrc2_pb21 7 to 0 isrc2_pb_byte_21[7:0] r/w 00h* reserved byte 21 (shall be set to a value of 0) 59h isrc2_pb22 7 to 0 isrc2_pb_byte_22[7:0] r/w 00h* reserved byte 22 (shall be set to a value of 0) 5ah isrc2_pb23 7 to 0 isrc2_pb_byte_23[7:0] r/w 00h* reserved byte 23 (shall be set to a value of 0) 5bh isrc2_pb24 7 to 0 isrc2_pb_byte_24[7:0] r/w 00h* reserved byte 24 (shall be set to a value of 0)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 94 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.7.3 audio content protection packet registers below is an example of use. please refer to hdmi 1.2a speci?cation for the correct de?nition of data bytes. see hdmi 1.2a speci?cation, section 9.3 for rules regarding the use of acp packets. 5ch isrc2_pb25 7 to 0 isrc2_pb_byte_25[7:0] r/w 00h* reserved byte 25 (shall be set to a value of 0) 5dh isrc2_pb26 7 to 0 isrc2_pb_byte_26[7:0] r/w 00h* reserved byte 26 (shall be set to a value of 0) 5eh isrc2_pb27 7 to 0 isrc2_pb_byte_27[7:0] r/w 00h* reserved byte 27 (shall be set to a value of 0) table 104. isrc2 packet registers (address 40h to 5eh) bit description continued legend: * = default value address register bit symbol access value description table 105. acp packet registers (address 60h to 7eh) bit description legend: * = default value address register bit symbol access value description 60h acp_ packet_ type 7 to 0 acp_packet_ type[7:0] r/w 04h* audio content protection packet type : packet type of the audio content protection packet 61h acp_type 7 to 0 acp_type[7:0] r/w 00h* audio content protection type: content protection type 62h acp_rsvd 7 to 0 acp_rsvd[7:0] r/w 00h* audio content protection reserved: reserved (shall be zero) 63h acp_pb0 7 to 0 acp_pb_byte_0[7:0] r/w 00h* audio content protection data byte 0 acp_type = 2: dvd-audio dvd-audio_type_dependent_ generation [8 bits] identi?es the generation of the dvd-audio-speci?c acp_type_ dependent ?elds. shall be set to logic 1. acp_type = 3: super audio cd cci_1_b0[7:0]
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 95 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter audio content protection data byte 1 64h acp_pb1 7 to 6 acp_pb_byte_1[7:6] r/w 00* acp_type = 2: dvd audio copy_permission[1:0] = audio_copy_permission parameter acp_type = 3: super audio cd cci_1_b1[7:6] 5 to 3 acp_pb_byte_1[5:3] r/w 000* acp_type = 2: dvd audio copy_number[2:0] = audio_copy_number parameter acp_type = 3: super audio cd cci_1_b1[5:3] 2 to 1 acp_pb_byte_1[2:1] r/w 00* acp_type = 2: dvd audio quality[1:0] = audio_quality parameter acp_type = 3: super audio cd cci_1_b1[2:1] 0 acp_pb_byte_1[0] r/w 0* acp_type = 2: dvd audio transaction = audio_transaction parameter acp_type = 3: super audio cd cci_1_b1[0] 65h acp_pb2 7 to 0 acp_pb_byte_2[7:0] r/w 00h* audio content protection data byte 2 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b2[7:0] 66h acp_pb3 7 to 0 acp_pb_byte_3[7:0] r/w 00h* audio content protection data byte 3 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b3[7:0] 67h acp_pb4 7 to 0 acp_pb_byte_4[7:0] r/w 00h* audio content protection data byte 4 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b4[7:0] 68h acp_pb5 7 to 0 acp_pb_byte_5[7:0] r/w 00h* audio content protection data byte 5 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b5[7:0] table 105. acp packet registers (address 60h to 7eh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 96 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 69h acp_pb6 7 to 0 acp_pb_byte_6[7:0] r/w 00h* audio content protection data byte 6 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b6[7:0] 6ah acp_pb7 7 to 0 acp_pb_byte_7[7:0] r/w 00h* audio content protection data byte 7 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b7[7:0] 6bh acp_pb8 7 to 0 acp_pb_byte_8[7:0] r/w 00h* audio content protection data byte 8 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b8[7:0] 6ch acp_pb9 7 to 0 acp_pb_byte_9[7:0] r/w 00h* audio content protection data byte 9 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b9[7:0] 6dh acp_pb10 7 to 0 acp_pb_byte_10[7:0] r/w 00h* audio content protection data byte 10 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b10[7:0] 6eh acp_pb11 7 to 0 acp_pb_byte_11[7:0] r/w 00h* audio content protection data byte 11 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b11[7:0] 6fh acp_pb12 7 to 0 acp_pb_byte_12[7:0] r/w 00h* audio content protection data byte 12 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b12[7:0] 70h acp_pb13 7 to 0 acp_pb_byte_13[7:0] r/w 00h* audio content protection data byte 13 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b13[7:0] table 105. acp packet registers (address 60h to 7eh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 97 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 71h acp_pb14 7 to 0 acp_pb_byte_14[7:0] r/w 00h* audio content protection data byte 14 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b14[7:0] 72h acp_pb15 7 to 0 acp_pb_byte_15[7:0] r/w 00h* audio content protection data byte 15 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b15[7:0] 73h acp_pb16 7 to 0 acp_pb_byte_16[7:0] r/w 00h* audio content protection data byte 16 acp_type = 2: dvd audio reserved (0) acp_type = 3: super audio cd cci_1_b16[7:0] 74h acp_pb17 7 to 0 acp_pb_byte_17[7:0] r/w 00h* audio content protection data byte 17 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) 75h acp_pb18 7 to 0 acp_pb_byte_18[7:0] r/w 00h* audio content protection data byte 18 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) 76h acp_pb19 7 to 0 acp_pb_byte_19[7:0] r/w 00h* audio content protection data byte 19 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) 77h acp_pb20 7 to 0 acp_pb_byte_20[7:0] r/w 00h* audio content protection data byte 20 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) 78h acp_pb21 7 to 0 acp_pb_byte_21[7:0] r/w 00h* audio content protection data byte 21 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) 79h acp_pb22 7 to 0 acp_pb_byte_22[7:0] r/w 00h* audio content protection data byte 22 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) table 105. acp packet registers (address 60h to 7eh) bit description continued legend: * = default value address register bit symbol access value description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 98 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.7.4 current page address register 9.8 hdmi and dvi page register de?nitions the current page address for the hdmi and dvi page is 12h. the con?guration of the registers for this page is given in t ab le 107 . 7ah acp_pb23 7 to 0 acp_pb_byte_23[7:0] r/w 00h* audio content protection data byte 23 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) 7bh acp_pb24 7 to 0 acp_pb_byte_24[7:0] r/w 00h* audio content protection data byte 24 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) 7ch acp_pb25 7 to 0 acp_pb_byte_25[7:0] r/w 00h* audio content protection data byte 25 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) 7dh acp_pb26 7 to 0 acp_pb_byte_26[7:0] r/w 00h* audio content protection data byte 26 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) 7eh acp_pb27 7 to 0 acp_pb_byte_27[7:0] r/w 00h* audio content protection data byte 27 acp_type = 2: dvd audio or acp_type = 3: super audio cd reserved (0) table 105. acp packet registers (address 60h to 7eh) bit description continued legend: * = default value address register bit symbol access value description table 106. curpage_adr register (address ffh) bit description legend: * = default value bit symbol access value description 7 to 0 curpage_adr[7:0] w 00h* current page address: selects the current memory page
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 99 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] r: reading register w: writing register x: bit must be set to default value for proper operation -: not used table 107. i 2 c-bus registers of memory page 12h [1] register sub addr r/w bit default value 7 (msb) 6 5 4 3 2 1 0 (lsb) not used 00h - - 0000 0000 ::: : : not used b7h - - 0000 0000 hdcp_tx33 b8h r/w x x x x x x hdmi x 0000 0000 not used b9h - - 0000 0000 ::: : : not used feh - - 0000 0000 curpage_adr ffh w curpage_adr[7:0] 0000 0000
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 100 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 9.8.1 hdmi control registers 9.8.2 current page address register 10. limiting values 11. thermal characteristics table 108. hdcp_tx33 register (address b8h) bit description legend: * = default value bit symbol access value description 7 to 6 x r/w 0000 00* unde?ned 1 hdmi r/w hdmi 0* dvi mode 1 hdmi mode 0 x r/w 0* unde?ned table 109. curpage_adr register (address ffh) bit description legend: * = default value bit symbol access value description 7 to 0 curpage_adr[7:0] w 00h* current page address: selects the current memory page table 110. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) - 0.5 +4.6 v v dd(1v8) supply voltage (1.8 v) - 0.5 +2.5 v d v dd supply voltage difference - 0.5 +0.5 v t stg storage temperature - 55 +150 c t amb ambient temperature 0 70 c t j junction temperature - 125 c v esd electrostatic discharge voltage hbm - 1500 +1500 v table 111. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air; jedec 4l board 26.5 k/w r th(j-c) thermal resistance from junction to case 10.2 k/w
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 101 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 12. static characteristics [1] the v ddd(3v3) and v ddc(1v8) power supplies must always follow the sequence shown in figure 14 to ensure proper power-up conditions. [2] worst case video format: a) input 480p (yc b c r 4 : 2 : 2 semi-planar) b) output 720p (yc b c r 4 : 2 : 2) [3] video format: a) input 480p (itu656 embedded sync, rising edge) b) output 1080i (yc b c r 4 : 2 : 2) [4] video format: a) input 1080p (rgb 4 : 4 : 4 external sync, rising edge) table 112. supplies v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 70 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit TDA9983Bhw/8 and TDA9983Bhw/15 v dda(fro_3v3) free running oscillator 3.3 v analog supply voltage 3.0 3.3 3.6 v v dda(pll_3v3) pll 3.3 v analog supply voltage 3.0 3.3 3.6 v v ddh(3v3) hdmi supply voltage (3.3 v) 3.0 3.3 3.6 v v ddd(3v3) digital supply voltage (3.3 v) [1] 3.0 3.3 3.6 v v ddc(1v8) core supply voltage (1.8 v) [1] 1.65 1.8 1.95 v TDA9983Bhw/8; up to 81 mhz i dda(fro_3v3) free running oscillator 3.3 v analog supply current - 0 1 ma i dda(pll_3v3) pll 3.3 v analog supply current [2] - 4.5 6 ma i ddd(3v3) digital supply current (3.3 v) - - 5 ma i ddh(3v3) hdmi supply current (3.3 v) - 14 16.5 ma i ddc(1v8) core supply current (1.8 v) [2] - 154.5 200 ma f clk(max) maximum clock frequency [3] 81 - - mhz p cons power consumption [3] - 322 - mw worst case [2] - 338 503 mw p tot total power dissipation [3] - 458 - mw worst case [2] - 472 651 mw p pd power dissipation in power-down mode - 13.5 38.4 mw TDA9983Bhw/15; up to 150 mhz i dda(fro_3v3) free running oscillator 3.3 v analog supply current - 0 1 ma i dda(pll_3v3) pll 3.3 v analog supply current [4] - 45ma i ddd(3v3) digital supply current (3.3 v) - - 5 ma i ddh(3v3) hdmi supply current (3.3 v) - 14 16.5 ma i ddc(1v8) core supply current (1.8 v) [4] - 167 210 ma f clk(max) maximum clock frequency [4] 150 - - mhz p cons power consumption [4] - 361 583 mw p tot total power dissipation [4] - 495 732 mw p pd power dissipation in power-down mode - 13.5 38.4 mw
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 102 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter b) output 1080p (rgb 4 : 4 : 4) table 113. lv-ttl digital inputs and outputs v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 70 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit not 5 v tolerant inputs: pins hsync, vsync, ap[7:0], aclk, tm, a0, a1, vpa[7:0], vpb[7:0], vpc[7:0], vclk, de and rst_n v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v i il low-level input current - 1- +1 m a i ih high-level input current - 1- +1 m a c i input capacitance - 4.5 - pf 5 v tolerant input: pin hpd v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v c i input capacitance - 4.5 - pf output: pin int v ol low-level output voltage c l = 10 pf; i ol = 2 ma - - 0.4 v table 114. tmds outputs v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 70 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit tmds output pins: tx0 - , tx0+, tx1 - , tx1+, tx2 - , tx2+, txc - and txc+ v o(p-p) peak-to-peak output voltage single output; r ext = 610 w (1 % tolerance) with test load and operating condition as in hdmi 1.2a speci?cation 400 525 600 mv v oh high-level output voltage 3.125 3.3 3.475 v v ol low-level output voltage 2.535 2.8 3.065 v
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 103 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 13. dynamic characteristics table 115. timing characteristics v dda(fro_3v3) = 3.0 v to 3.6 v; v dda(pll_3v3) = 3.0 v to 3.6 v; v ddh(3v3) = 3.0 v to 3.6 v; v ddd(3v3) = 3.0 v to 3.6 v; v ddc(1v8) = 1.65 v to 1.95 v; v pp = 0 v; t amb = 0 c to 70 c. typical values are measured at v dda(fro_3v3) = v dda(pll_3v3) = v ddh(3v3) = v ddd(3v3) = 3.3 v; v ddc(1v8) = 1.8 v; v pp = 0 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies: pins v ddc(1v8) , v ddd(3v3) ; see figure 14 t d delay time 1 - - ms clock inputs: pins vclk, vpa[7:0], vpb[7:0], vpc[7:0]; see figure 15 , 16 , 17 , 18 and 19 f clk(max) maximum clock frequency TDA9983Bhw/8 81 - - mhz TDA9983Bhw/15 150 - - mhz t su(d) data input set-up time - 1.3 - - ns t h(d) data input hold time 3.6 - - ns d clk clock duty cycle 40 - 60 % ddc i 2 c-bus; 5 v tolerant; master bus: pins ddc_sda and ddc_scl f scl scl clock frequency standard mode - - 100 khz i 2 c-bus; 5 v tolerant; master bus: pins i2c_sda and i2c_scl f scl scl clock frequency standard mode - - 100 khz fast mode - - 400 khz tmds output pins: txc - and txc+ f clk(max) maximum clock frequency TDA9983Bhw/8 81 - - mhz TDA9983Bhw/15 150 - - mhz tmds output pins: tx0 - , tx0+, tx1 - , tx1+, tx2 - and tx2+ f clk(max) maximum clock frequency TDA9983Bhw/8 810 - - mhz TDA9983Bhw/15 1.5 - - ghz fig 14. power supply sequencing 001aag259 50 % 27 % t d 3 0 s 1.8 v 3.3 v
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 104 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 13.1 input format in t ab le 116 the port vpa has been mapped to c b (yuv space)/b (rgb space), vpb has been mapped to y (yuv space)/g (rgb space) and vpc has been mapped to c r (yuv space)/r (rgb space). [1] register vip_cntrl_0 = 23h; vip_cntrl_1 = 45h; vip_cntrl_2 = 01h. [2] register vip_cntrl_0 = 23h; vip_cntrl_1 = 45h; vip_cntrl_2 = 01h. [3] register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 14h. [4] register vip_cntrl_0 = 23h; vip_cntrl_1 = 50h; vip_cntrl_2 = 00h. table 116. input format input pins signal rgb yuv 4:4:4 [1] 4:4:4 [2] 4:2:2 (semi-planar) [3] 4 : 2 : 2: (itu656-like) [4] video port a vpa[0] c b [0]/b[0] b[0] c b [0] y 0 [0] y 1 [0] c b [0] y 0 [0] c r [0] y 1 [0] vpa[1] c b [1]/b[1] b[1] c b [1] y 0 [1] y 1 [1] c b [1] y 0 [1] c r [1] y 1 [1] vpa[2] c b [2]/b[2] b[2] c b [2] y 0 [2] y 1 [2] c b [2] y 0 [2] c r [2] y 1 [2] vpa[3] c b [3]/b[3] b[3] c b [3] y 0 [3] y 1 [3] c b [3] y 0 [3] c r [3] y 1 [3] vpa[4] c b [4]/b[4] b[4] c b [4] c b [0] c r [0] llll vpa[5] c b [5]/b[5] b[5] c b [5] c b [1] c r [1] llll vpa[6] c b [6]/b[6] b[6] c b [6] c b [2] c r [2] llll vpa[7] c b [7]/b[7] b[7] c b [7] c b [3] c r [3] llll video port b vpb[0] y[0]/g[0] g[0] y[0] y 0 [4] y 1 [4] c b [4] y 0 [4] c r [4] y 1 [4] vpb[1] y[1]/g[1] g[1] y[1] y 0 [5] y 1 [5] c b [5] y 0 [5] c r [5] y 1 [5] vpb[2] y[2]/g[2] g[2] y[2] y 0 [6] y 1 [6] c b [6] y 0 [6] c r [6] y 1 [6] vpb[3] y[3]/g[3] g[3] y[3] y 0 [7] y 1 [7] c b [7] y 0 [7] c r [7] y 1 [7] vpb[4] y[4]/g[4] g[4] y[4] y 0 [8] y 1 [8] c b [8] y 0 [8] c r [8] y 1 [8] vpb[5] y[5]/g[5] g[5] y[5] y 0 [9] y 1 [9] c b [9] y 0 [9] c r [9] y 1 [9] vpb[6] y[6]/g[6] g[6] y[6] y 0 [10] y 1 [10] c b [10] y 0 [10] c r [10] y 1 [10] vpb[7] y[7]/g[7] g[7] y[7] y 0 [11] y 1 [11] c b [11] y 0 [11] c r [11] y 1 [11] video port c vpc[0] c r [0]/r[0] r[0] c r [0] c b [4] c r [4] llll vpc[1] c r [1]/r[1] r[1] c r [1] c b [5] c r [5] llll vpc[2] c r [2]/r[2] r[2] c r [2] c b [6] c r [6] llll vpc[3] c r [3]/r[3] r[3] c r [3] c b [7] c r [7] llll vpc[4] c r [4]/r[4] r[4] c r [4] c b [8] c r [8] llll vpc[5] c r [5]/r[5] r[5] c r [5] c b [9] c r [9] llll vpc[6] c r [6]/r[6] r[6] c r [6] c b [10] c r [10] l l l l vpc[7] c r [7]/r[7] r[7] c r [7] c b [11] c r [11] l l l l
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 105 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 13.2 example of supported video the TDA9983B supports all eia/cea-861b, atsc video input formats. table 117. timing parameters for eia/cea-861b format nr. format v frequency (hz) h total v total h frequency (khz) pixel frequency (mhz) pixel repetition scaler 59.94 hz systems 1 (vga) 640 480p 59.9401 800 525 31.4685 25.174825 1 - 2, 3 720 480p 59.9401 858 525 31.4685 27 1 x 4 1280 720p 59.9401 1650 750 44.955 74.175824 1 - 5 1920 1080i 59.9401 2200 1125 33.7163 74.175824 1 - 6, 7 (ntsc) 720 480i 59.9401 858 525 15.7343 13.5 2 x 8, 9 720 240p 59.9401 858 262 15.7043 13.474286 2 - 8, 9 720 240p 59.9401 858 263 15.7642 13.525714 2 - 10, 11 720 480i 59.9401 858 525 15.7343 13.5 4, 5, 7 [1] , 8 [1] , 10 [1] - 12, 13 720 240p 59.9401 858 262 15.7043 13.474286 4, 5, 7 [1] , 8 [1] , 10 [1] - 12, 13 720 240p 59.9401 858 263 15.7642 13.525714 4, 5, 7 [1] , 8 [1] , 10 [1] - 14, 15 1440 480p 59.9401 1716 525 31.4685 54 2 - 16 [1] 1920 1080p 59.9401 2200 1125 67.4326 148.35165 [1] 1- 60 hz systems 1 (vga) 640 480p 60 800 525 31.5 25.2 1 - 2, 3 720 480p 60 858 525 31.5 27.27 1 x 4 1280 720p 60 1650 750 45 74.25 1 - 5 1920 1080i 60 2200 1125 33.75 74.25 1 - 6, 7 (ntsc) 720 480i 60 858 525 15.75 13.5135 2 x 8, 9 720 240p 60 858 262 15.72 13.48776 2 - 8, 9 720 240p 60 858 263 15.78 13.53924 2 - 10, 11 720 480i 60 858 525 15.75 13.5135 4, 5, 7 [1] , 8 [1] , 10 [1] - 12, 13 720 240p 60 858 262 15.72 13.48776 4, 5, 7 [1] , 8 [1] , 10 [1] - 12, 13 720 240p 60 858 263 15.78 13.53924 4, 5, 7 [1] , 8 [1] , 10 [1] - 14, 15 1440 480p 60 1716 525 31.5 54.054 2 - 16 [1] 1920 1080p 60 2200 1125 67.5 148.5 [1] 1- 50 hz systems 17, 18 720 576p 50 864 625 31.25 27 1 x 19 1280 720p 50 1980 750 37.5 74.25 1 - 20 1920 1080i 50 2640 1125 28.125 74.25 1 - 21, 22 (pal) 720 576i 50 864 625 15.625 13.5 1 x 23, 24 720 288p 50 864 312 15.6 13.4784 2 - 23, 24 720 288p 50 864 313 15.65 13.5216 2 -
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 106 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] only for TDA9983Bhw/15. 23, 24 720 288p 50 864 314 15.7 13.5648 2 - 25, 26 720 576i 50 864 625 15.625 13.5 4, 5, 7 [1] , 8 [1] , 10 [1] - 27, 28 720 288p 50 864 312 15.6 13.4784 4, 5, 7 [1] , 8 [1] , 10 [1] - 27, 28 720 288p 50 864 313 15.65 13.5216 4, 5, 7 [1] , 8 [1] , 10 [1] - 27, 28 720 288p 50 864 314 15.7 13.5648 2 - 29, 30 1440 576p 50 1728 625 31.25 54 1 - 31 [1] 1920 1080p 50 2640 1125 56.25 148.5 [1] 1- various systems 32 1920 1080p 23.976 2750 1125 26.973 74.175824 1 - 32 1920 1080p 24 2750 1125 27 74.25 1 - 33 1920 1080p 25 2640 1125 28.125 74.25 1 - 34 1920 1080p 29.97 2200 1125 33.716 74.175824 1 - 34 1920 1080p 30 2200 1125 33.75 74.25 1 - table 117. timing parameters for eia/cea-861b continued format nr. format v frequency (hz) h total v total h frequency (khz) pixel frequency (mhz) pixel repetition scaler table 118. timing parameters for pc standards below 150 mhz standard format v frequency (hz) h total v total h frequency (khz) pixel frequency (mhz) pixel repetition scaler vga 640 350p 85.08 832 445 37.8606 31.5000192 - - 640 400p 85.08 832 445 37.8606 31.5000192 - - 720 400p 85.039 936 446 37.927394 35.50004078 - - 640 480p 59.94005994 800 525 31.46853147 25.17482517 - - 640 480p 72.809 832 520 37.86068 31.50008576 - - 640 480p 75 840 500 37.5 31.5 - - 640 480p 85.008 832 509 43.269072 35.9998679 - - svga 800 600p 56.250 1024 625 35.15625 36 - - 800 600p 60.317 1056 628 37.879076 40.00030426 - - 800 600p 72.188 1040 666 48.077208 50.00029632 - - 800 600p 75.000 1056 625 46.875 49.5 - - 800 600p 85.061 1048 631 53.673491 56.24981857 - -
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 107 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter [1] only for TDA9983Bhw/15. 13.3 timing diagrams xga 1024 786p 60.004 1344 806 48.363224 65.00017306 - - 1024 786p 70.069 1328 806 56.475614 74.99961539 - - 1024 786p 75.029 1312 800 60.0232 78.7504384 - - 1024 786p [1] 84.997 1376 808 68.677576 94.50034458 - - 1024 786i 86.957 1264 817 35.5219345 44.89972521 - - 1152 864p [1] 75.000 1600 900 67.5 108 - - 1152 864p [1] 84.999 1576 907 77.094093 121.5002906 - - 1280 960p [1] 60 1800 1000 60 108 - - 1280 960p [1] 85.002 1728 1011 85.937022 148.499174 - - sxga [1] 1280 1024p [1] 60.020 1688 1066 63.98132 108.0004682 - - 1280 1024p [1] 75.025 1688 1066 79.97665 135.0005852 - - table 118. timing parameters for pc standards below 150 mhz continued standard format v frequency (hz) h total v total h frequency (khz) pixel frequency (mhz) pixel repetition scaler fig 15. timing in rgb 4:4:4 (rising edge) input 001aag250 bxxx bxxx ... b3 b2 b1 b0 hsync/href vsync/vref de/fref gxxx gxxx ... g3 g2 g1 g0 rxxx rxxx ... r3 r2 r1 r0 t clk(h) t clk(l) t h(d) t su(d) control inputs vpa[7:0] vclk vpb[7:0] vpc[7:0]
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 108 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter fig 16. timing in yc b c r 4 : 4 : 4 (rising edge) input 001aag251 c b xxx c b xxx ... c b 3 c b 2 c b 1 c b 0 hsync/href vsync/vref de/fref yxxx yxxx ... y3 y2 y1 y0 c r xxx c r xxx ... c r 3 c r 2 c r 1 c r 0 t clk(h) t clk(l) t h(d) t su(d) control inputs vpa[7:0] vclk vpb[7:0] vpc[7:0] fig 17. timing yc b c r 4 : 2 : 2 itu656-like double edge (rising and falling) input 001aag252 c r xxx yxxx ... y1 c r 0 y0 c b 0 hsync/href vsync/vref de/fref t clk(h) t clk(l) t h(d) t su(d) control inputs vpb[7:0]; vpa[3:0] vclk t h(d) t su(d) fig 18. timing yc b c r 4 : 2 : 2 itu656-like single edge external (rising edge) input 001aag253 c r xxx yxxx ... y1 c r 0 y0 c b 0 hsync/href vsync/vref de/fref t clk(h) t clk(l) t h(d) t su(d) control inputs vpb[7:0]; vpa[3:0] vclk
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 109 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter fig 19. timing yc b c r 4 : 2 : 2 semi-planar external synchronization (rising edge) input 001aag256 y5 ... y4 y3 y2 y1 y0 hsync/href vsync/vref de/fref c r 4 ... c b 4 c r 2 c b 2 c r 0 c b 0 t clk(h) t clk(l) control inputs vpb[7:0]; vpa[3:0] vclk vpc[7:0]; vpa[7:4] t h(d) t su(d)
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 110 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 14. application information fig 20. application diagram for set-top box 8 001aaf298 cvbs/y/(g) c/p b /(b) p r /(r) hdmi data stream dac dac adc g dsp aux data audio i 2 s-bus or s/pdif dac hdmi tx denc stereo audio dac lo fig 21. application diagram for dvd player 8 001aaf299 cvbs/y/(g) c/p b /(b) p r /(r) hdmi data stream dac dac dsp aux data audio i 2 s-bus or s/pdif dvd read engine dac hdmi tx scaler denc stereo audio dac fig 22. transmitter connection with external world 001aag260 microprocessor master mpeg2 decoder hdmi receiver/ repeater hdmi source slave hdmi clock hdmi channel 0 hdmi channel 1 hdmi channel 2 hot plug detect ddc (scl and sda) cec line e-edid slave address a0 slave master master reset digital video (up to 24 bits) sync signals audio, s/pdif and i 2 s-bus irq i 2 c-bus i 2 c-bus hdmi TDA9983B
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 111 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 15. package outline fig 23. package outline sot841-4 (htqfp80) references outline version european projection issue date iec jedec jeita sot841-4 ms-026 sot841-4 06-04-25 06-06-20 note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included unit a max mm 1.2 0.15 0.05 1.05 0.95 0.27 0.17 0.20 0.09 12.1 11.9 12.1 11.9 14.15 13.85 14.15 13.85 0.75 0.45 1.45 1.05 1.45 1.05 a 1 dimensions (mm are the original dimensions) htqfp80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad 80 21 61 40 120 60 41 b p b p d h d eh e b a d h e h y z d z e e e w m w m pin 1 index vb m va m c exposed die pad x q a l p detail x l (a 3 ) a 2 a 1 0 5 10 mm scale a 2 a 3 0.25 b p c d (1) e (1) e 0.5 h d 4.79 4.69 d h 4.79 4.69 e h h e l 1 l p v 0.2 w 0.08 y 0.1 z d (1) z e (1) q 7 0
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 112 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 16.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 113 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 16.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 24 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 119 and 120 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 24 . table 119. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 120. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 114 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 17. soldering: additional information the package of this device supports the re?ow soldering process only. 18. abbreviations msl: moisture sensitivity level fig 24. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 121. abbreviations acronym description aac advanced audio coding ac-3 active coding-3 acp audio content protection adc analog-to-digital converter afd active format descriptor atrac adaptive transform acoustic coding av audio video cec consumer electronic control cmos complimentary metal-oxide semiconductor cts cycle time stamp dac digital-to-analog converter ddc display data channel denc digital video encoder dsc distributed source code dsp digital signal processor dts digital transmission system
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 115 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter dvb digital video broadcast dvc digital video camera dvd digital versatile disc dvi digital visual interface d-vhs data-vhs eav end active video edid rom extended display identi?cation data rom e-edid enhanced extended display identi?cation data fifo first in first out hbm human body model hdcp high-bandwidth digital content protection hdd hard-disk drive hdmi high-de?nition multimedia interface hdtv high-de?nition television hpd hot plug detect id identi?er irq interrupt request isrc international standard recording code ksv key selection vector lo local oscillator l-pcm linear pulse code modulation lsb least signi?cant bit lut look-up table lv-ttl low voltage transistor-transistor logic msb most signi?cant bit pal phase alternating line pcm pulse-code modulation pll phase-locked loop pvr personal video recorder rgb red green blue rx receiver sav start active video stb set-top box s/pdif sony/philips digital interface tmds transition minimized differential signalling tx transmitter upc/ean universal product code/european assistance network (gs1) yuv y = luminance, u = normalized blue, v = normalized red yc b c r y = luminance, c b = chroma component blue, c r = chroma component red table 121. abbreviations continued acronym description
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 116 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 19. revision history table 122. revision history document id release date data sheet status change notice supersedes TDA9983B_1 20080520 product data sheet - -
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 117 of 119 nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 20.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 20.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. quick reference data the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 20.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
TDA9983B_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 20 may 2008 118 of 119 continued >> nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 8 8.1 system clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 video input processor . . . . . . . . . . . . . . . . . . . . 8 8.3 synchronization . . . . . . . . . . . . . . . . . . . . . . . 18 8.3.1 timing extraction generator . . . . . . . . . . . . . . 18 8.3.2 data enable generator . . . . . . . . . . . . . . . . . . 18 8.4 input and output video format . . . . . . . . . . . . . 18 8.5 upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.6 color space converter. . . . . . . . . . . . . . . . . . . 19 8.7 downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8 audio input format. . . . . . . . . . . . . . . . . . . . . . 19 8.9 s/pdif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.10 i 2 s-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.11 power management . . . . . . . . . . . . . . . . . . . . 20 8.12 interrupt controller . . . . . . . . . . . . . . . . . . . . . 20 8.13 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.14 hdmi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.1 output hdmi buffers . . . . . . . . . . . . . . . . . . . . 21 8.14.2 pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.3 hdmi and dvi receiver discrimination . . . . . . 21 8.14.4 ddc channel . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.4.1 e-edid reading. . . . . . . . . . . . . . . . . . . . . . . . 21 8.15 scaler unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.16 input and output video scaler . . . . . . . . . . . . . 22 8.17 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . 22 9i 2 c-bus register de?nitions . . . . . . . . . . . . . . . 23 9.1 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 memory page management . . . . . . . . . . . . . . 23 9.3 general control page register de?nitions . . . . 23 9.3.1 main control register . . . . . . . . . . . . . . . . . . . . 29 9.3.2 interrupt ?ags/masks registers . . . . . . . . . . . . 29 9.3.3 video input processing control registers. . . . . 30 9.3.4 color space conversion registers . . . . . . . . . . 34 9.3.5 video format registers. . . . . . . . . . . . . . . . . . . 36 9.3.6 hdmi video formatter control registers . . . . . . 40 9.3.7 timer control registers . . . . . . . . . . . . . . . . . . 42 9.3.8 ndiv register . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.3.9 control registers. . . . . . . . . . . . . . . . . . . . . . . 42 9.3.10 current page address register . . . . . . . . . . . . 43 9.4 scaler page register de?nitions . . . . . . . . . . . 43 9.4.1 scaler control registers . . . . . . . . . . . . . . . . . 48 9.4.2 scaling input time base generator control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.4.3 current page address register . . . . . . . . . . . . 55 9.5 pll settings page register de?nitions . . . . . . 55 9.5.1 pll serial registers . . . . . . . . . . . . . . . . . . . . 57 9.5.2 current page address register . . . . . . . . . . . . 63 9.6 information frames and packets page register de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.6.1 vendor-speci?c infoframe registers. . . . . . . . 70 9.6.2 auxiliary video information infoframe registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.6.3 source product description infoframe registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.6.4 audio infoframe registers . . . . . . . . . . . . . . . 76 9.6.5 mpeg source infoframe registers . . . . . . . . . 79 9.6.6 current page address register . . . . . . . . . . . . 81 9.7 audio settings and content info packets page register de?nitions . . . . . . . . . . . . . . . . . . . . . 81 9.7.1 audio input processor control registers . . . . . 87 9.7.2 isrc packets registers. . . . . . . . . . . . . . . . . . 91 9.7.3 audio content protection packet registers . . . 94 9.7.4 current page address register . . . . . . . . . . . . 98 9.8 hdmi and dvi page register de?nitions . . . . . 98 9.8.1 hdmi control registers . . . . . . . . . . . . . . . . . 100 9.8.2 current page address register . . . . . . . . . . . 100 10 limiting values . . . . . . . . . . . . . . . . . . . . . . . 100 11 thermal characteristics . . . . . . . . . . . . . . . . 100 12 static characteristics . . . . . . . . . . . . . . . . . . 101 13 dynamic characteristics . . . . . . . . . . . . . . . . 103 13.1 input format . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.2 example of supported video . . . . . . . . . . . . 105 13.3 timing diagrams. . . . . . . . . . . . . . . . . . . . . . 107 14 application information . . . . . . . . . . . . . . . . 110 15 package outline . . . . . . . . . . . . . . . . . . . . . . . 111 16 soldering of smd packages . . . . . . . . . . . . . 112 16.1 introduction to soldering. . . . . . . . . . . . . . . . 112 16.2 wave and re?ow soldering . . . . . . . . . . . . . . 112 16.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . 112 16.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . 113 17 soldering: additional information . . . . . . . . 114 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 114
nxp semiconductors TDA9983B 150 mhz pixel rate hdmi transmitter ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 20 may 2008 document identifier: TDA9983B_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 116 20 legal information. . . . . . . . . . . . . . . . . . . . . . 117 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 117 20.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 117 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 117 21 contact information. . . . . . . . . . . . . . . . . . . . 117 22 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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